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tak.sugawa |
EDA Netlist Writer report for yacc
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Thu Apr 14 20:22:40 2005
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Version 4.2 Build 178 01/19/2005 Service Pack 1 SJ Web Edition
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; Table of Contents ;
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1. Legal Notice
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2. EDA Netlist Writer Summary
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3. Simulation Tool Settings
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4. Simulation Tool Generated Files
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5. EDA Netlist Writer Messages
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----------------
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; Legal Notice ;
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----------------
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Copyright (C) 1991-2005 Altera Corporation
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Any megafunction design, and related netlist (encrypted or decrypted),
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support information, device programming or simulation file, and any other
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associated documentation or information provided by Altera or a partner
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under Altera's Megafunction Partnership Program may be used only
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to program PLD devices (but not masked PLD devices) from Altera. Any
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other use of such megafunction design, netlist, support information,
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device programming or simulation file, or any other related documentation
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or information is prohibited for any other purpose, including, but not
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limited to modification, reverse engineering, de-compiling, or use with
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any other silicon devices, unless such use is explicitly licensed under
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a separate agreement with Altera or a megafunction partner. Title to the
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intellectual property, including patents, copyrights, trademarks, trade
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secrets, or maskworks, embodied in any such megafunction design, netlist,
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support information, device programming or simulation file, or any other
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related documentation or information provided by Altera or a megafunction
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partner, remains with Altera, the megafunction partner, or their respective
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licensors. No other licenses, including any licenses needed under any third
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party's intellectual property, are provided herein.
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+-------------------------------------------------------------------+
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; EDA Netlist Writer Summary ;
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+---------------------------+---------------------------------------+
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; EDA Netlist Writer Status ; Successful - Thu Apr 14 20:22:40 2005 ;
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; Revision Name ; yacc ;
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; Top-level Entity Name ; yacc ;
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; Family ; Stratix II ;
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; Simulation Tool Writer ; Successful ;
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+---------------------------+---------------------------------------+
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+---------------------------------------------------------------------------+
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; Simulation Tool Settings ;
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+------------------------------------------------------+--------------------+
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; Option ; Setting ;
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+------------------------------------------------------+--------------------+
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; Tool Name ; Custom Verilog HDL ;
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; Generate Netlist for Functional Simulation Only ; Off ;
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; Time scale ; 1 ps ;
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; Truncate long hierarchy paths ; Off ;
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; Map illegal Verilog HDL characters ; Off ;
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; Flatten buses into individual nodes ; Off ;
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; Maintain hierarchy ; Off ;
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; Bring out device-wide set/reset signals as ports ; Off ;
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; Output Excalibur stripe as a single module or entity ; Off ;
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; Enable glitch filtering ; Off ;
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+------------------------------------------------------+--------------------+
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+---------------------------------------------------------+
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; Simulation Tool Generated Files ;
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+---------------------------------------------------------+
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; Generated Files ;
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+---------------------------------------------------------+
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; F:/yacc/syn/altra_stratix2/simulation/custom/yacc.vo ;
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; F:/yacc/syn/altra_stratix2/simulation/custom/yacc_v.sdo ;
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+---------------------------------------------------------+
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+-----------------------------+
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; EDA Netlist Writer Messages ;
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+-----------------------------+
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Info: *******************************************************************
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Info: Running Quartus II EDA Netlist Writer
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Info: Version 4.2 Build 178 01/19/2005 Service Pack 1 SJ Web Edition
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Info: Processing started: Thu Apr 14 20:22:27 2005
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Info: Command: quartus_eda --lower_priority --import_settings_files=off --export_settings_files=off yacc -c yacc
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Info: Generated files "yacc.vo" and "yacc_v.sdo" in directory "F:/yacc/syn/altra_stratix2/simulation/custom/" for EDA simulation tool
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Info: Quartus II EDA Netlist Writer was successful. 0 errors, 0 warnings
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Info: Processing ended: Thu Apr 14 20:22:40 2005
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Info: Elapsed time: 00:00:14
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