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tak.sugawa |
Flow report for yacc
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Thu Apr 14 20:22:41 2005
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Version 4.2 Build 178 01/19/2005 Service Pack 1 SJ Web Edition
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---------------------
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; Table of Contents ;
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---------------------
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1. Legal Notice
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2. Flow Summary
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3. Flow Settings
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4. Flow Elapsed Time
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5. Flow Log
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----------------
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; Legal Notice ;
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----------------
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Copyright (C) 1991-2005 Altera Corporation
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Any megafunction design, and related netlist (encrypted or decrypted),
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support information, device programming or simulation file, and any other
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associated documentation or information provided by Altera or a partner
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under Altera's Megafunction Partnership Program may be used only
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to program PLD devices (but not masked PLD devices) from Altera. Any
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other use of such megafunction design, netlist, support information,
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device programming or simulation file, or any other related documentation
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or information is prohibited for any other purpose, including, but not
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limited to modification, reverse engineering, de-compiling, or use with
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any other silicon devices, unless such use is explicitly licensed under
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a separate agreement with Altera or a megafunction partner. Title to the
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intellectual property, including patents, copyrights, trademarks, trade
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secrets, or maskworks, embodied in any such megafunction design, netlist,
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support information, device programming or simulation file, or any other
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related documentation or information provided by Altera or a megafunction
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partner, remains with Altera, the megafunction partner, or their respective
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licensors. No other licenses, including any licenses needed under any third
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party's intellectual property, are provided herein.
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+-------------------------------------------------------------------------+
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; Flow Summary ;
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+--------------------------+----------------------------------------------+
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; Flow Status ; Successful - Thu Apr 14 20:22:40 2005 ;
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; Quartus II Version ; 4.2 Build 178 01/19/2005 SP 1 SJ Web Edition ;
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; Revision Name ; yacc ;
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; Top-level Entity Name ; yacc ;
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; Family ; Stratix II ;
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; Device ; EP2S15F484C3 ;
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; Timing Models ; Preliminary ;
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; Met timing requirements ; Yes ;
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; Total ALUTs ; 2,926 / 12,480 ( 23 % ) ;
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; Total registers ; 1136 ;
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; Total pins ; 53 / 343 ( 15 % ) ;
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; Total virtual pins ; 0 ;
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; Total memory bits ; 137,216 / 419,328 ( 32 % ) ;
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; DSP block 9-bit elements ; 8 / 96 ( 8 % ) ;
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; Total PLLs ; 0 / 6 ( 0 % ) ;
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; Total DLLs ; 0 / 2 ( 0 % ) ;
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+--------------------------+----------------------------------------------+
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+-----------------------------------------+
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; Flow Settings ;
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+-------------------+---------------------+
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; Option ; Setting ;
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+-------------------+---------------------+
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; Start date & time ; 04/14/2005 19:56:43 ;
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; Main task ; Compilation ;
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; Revision Name ; yacc ;
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+-------------------+---------------------+
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+-------------------------------------+
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; Flow Elapsed Time ;
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+----------------------+--------------+
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; Module Name ; Elapsed Time ;
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+----------------------+--------------+
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; Analysis & Synthesis ; 00:03:09 ;
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; Fitter ; 00:21:44 ;
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; Assembler ; 00:00:14 ;
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; Timing Analyzer ; 00:00:16 ;
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; EDA Netlist Writer ; 00:00:14 ;
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; Total ; 00:25:37 ;
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+----------------------+--------------+
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------------
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; Flow Log ;
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------------
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quartus_map --lower_priority --import_settings_files=on --export_settings_files=off yacc -c yacc
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quartus_fit --lower_priority --import_settings_files=off --export_settings_files=off yacc -c yacc
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quartus_asm --lower_priority --import_settings_files=off --export_settings_files=off yacc -c yacc
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quartus_tan --lower_priority --import_settings_files=off --export_settings_files=off yacc -c yacc --timing_analysis_only
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quartus_eda --lower_priority --import_settings_files=off --export_settings_files=off yacc -c yacc
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