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/*******************************************************************************

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*     (c) Copyright 1995-2004 Xilinx, Inc.                                     *

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*******************************************************************************/

// The synopsys directives "translate_off/translate_on" specified below are

// supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity synthesis

// tools. Ensure they are correct for your synthesis tool(s).

// You must compile the wrapper file fifo.v when simulating

// the core, fifo. When compiling the wrapper file, be sure to

// reference the XilinxCoreLib Verilog simulation library. For detailed

// instructions, please refer to the "CORE Generator Help".

`timescale 1ns/1ps

module fifo(

        clk,

        sinit,

        din,

        wr_en,

        rd_en,

        dout,

        full,

        empty);

input clk;

input sinit;

input [7 : 0] din;

input wr_en;

input rd_en;

output [7 : 0] dout;

output full;

output empty;

// synopsys translate_off

      SYNC_FIFO_V5_0 #(

                1,      // c_dcount_width

                0,       // c_enable_rlocs

                0,       // c_has_dcount

                0,       // c_has_rd_ack

                0,       // c_has_rd_err

                0,       // c_has_wr_ack

                0,       // c_has_wr_err

                1,      // c_memory_type

                0,       // c_ports_differ

                1,      // c_rd_ack_low

                1,      // c_rd_err_low

                8,      // c_read_data_width

                512,    // c_read_depth

                8,      // c_write_data_width

                512,    // c_write_depth

                1,      // c_wr_ack_low

                1)      // c_wr_err_low

        inst (

                .CLK(clk),

                .SINIT(sinit),

                .DIN(din),

                .WR_EN(wr_en),

                .RD_EN(rd_en),

                .DOUT(dout),

                .FULL(full),

                .EMPTY(empty),

                .RD_ACK(),

                .WR_ACK(),

                .RD_ERR(),

                .WR_ERR(),

                .DATA_COUNT());

// synopsys translate_on

// FPGA Express black box declaration

// synopsys attribute fpga_dont_touch "true"

// synthesis attribute fpga_dont_touch of fifo is "true"

// XST black box declaration

// box_type "black_box"

// synthesis attribute box_type of fifo is "black_box"

endmodule