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[/] [yacc/] [trunk/] [syn/] [xilinx/] [fifo.xco] - Blame information for rev 4

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Line No. Rev Author Line
1 2 tak.sugawa
# BEGIN Project Options
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SET flowvendor = Foundation_iSE
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SET vhdlsim = True
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SET verilogsim = True
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SET workingdirectory = F:\yacc\syn\xilinx
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SET speedgrade = -4
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SET simulationfiles = Behavioral
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SET asysymbol = True
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SET addpads = False
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# SET outputdirectory = F:\yacc\syn\xilinx
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SET device = xc3s200
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SET implementationfiletype = Edif
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SET busformat = BusFormatAngleBracketNotRipped
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SET foundationsym = False
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SET package = ft256
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SET createndf = False
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SET designentry = VHDL
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SET devicefamily = spartan3
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SET formalverification = False
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SET removerpms = False
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# END Project Options
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# BEGIN Select
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SELECT Synchronous_FIFO family Xilinx,_Inc. 5.0
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# END Select
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# BEGIN Parameters
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CSET memory_type=Block_Memory
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CSET write_acknowledge_flag=false
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CSET data_width=8
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CSET write_error_flag=false
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CSET read_acknowledge_sense=Active_Low
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CSET data_count_width=1
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CSET fifo_depth=512
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CSET component_name=fifo
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CSET data_count=false
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CSET read_acknowledge_flag=false
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CSET read_error_sense=Active_Low
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CSET read_error_flag=false
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CSET write_acknowledge_sense=Active_Low
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CSET write_error_sense=Active_Low
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# END Parameters
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GENERATE
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