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[/] [yacc/] [trunk/] [syn/] [xilinx/] [mul_div_module5.v] - Blame information for rev 4

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//Jun.2.2004
//Jun.27.2004
//Jun.28.2004
//Jun.30.2004 mulfunc output bug fix
//                         still 16x16 sign extension
//Jul.2.2004  mul 32x32=>64bit w/ w/o sign
//Jul.2.2004  address MUL_WIDTH==1
//Jul.4.2004  input critical path : => add carry_ff;
//Jul.5.2004                             :=> less fanout 
//Jul.13.2004 signed mul bug fix
//Jul.15.2004 32/32 div 
//Jul.16.2004 diet
//Jul.17.2004 add `ifdef less path delay for interface port
//Apr.7.2005 ADDRESS to XILINX Specific problem 
 
// mul/div module
 
// a[31:0] /b[31:0]  =>  
//   mul_div_out[15:0]  <=a/b
//   mul_div_out[31:16] <=a%b
// No detection of overflow
// Algorithm
//  answer_reg = (answer_reg << 1);
// multout_reg<={sum,a_reg[31]};
//    if (multout_reg >= b_reg) {
//       answer_reg += 1;
//       multout_reg -= b_reg;
//    }
//    a_reg <= a_reg << 1;
`include "define.h"
module mul_div(clock,sync_reset,a,b,mul_div_out,mul_div_sign,mul_div_word,mul_div_mode,state,stop_state,mul_div_enable,lohi);
`ifdef RAM4K
 
         `ifdef XILINX
                parameter MUL_WIDTH=16;//Must be 2,4,8,16 2=> less area less speed 16=> greater area but faster
                parameter MUL_STATE_MSB=2;//should be 32/MUL_WIDTH-1+1;
                // XILINX fails using ISE7.1 if MUL_WIDTH==1,2
                // if MULWIDTH==1 synthesis is possible but post synthesis simulation fails
            // if MULWIDTH==2 synthesis fails;
            // MUL_WIDTH==16 shows good.
 
         `else
                        parameter MUL_WIDTH=1;//Must be 2,4,8,16 2=> less area less speed 16=> greater area but faster
                        parameter MUL_STATE_MSB=32;//should be 32/MUL_WIDTH-1+1;
         `endif
`else
        `ifdef XILINX
                parameter MUL_WIDTH=16;//Must be 2,4,8,16 2=> less area less speed 16=> greater area but faster
                parameter MUL_STATE_MSB=2;//should be 32/MUL_WIDTH-1+1;
                // XILINX fails using ISE7.1 if MUL_WIDTH==1,2
                // if MULWIDTH==1 synthesis is possible but post synthesis simulation fails
                 // if MULWIDTH==2 synthesis fails;
             // MUL_WIDTH==16 shows good.
 
         `else
                parameter MUL_WIDTH=1;//Must be 2,4,8,16 2=> less area less speed 16=> greater area but faster
                parameter MUL_STATE_MSB=32;//should be 32/MUL_WIDTH-1+1;
                `endif
`endif
        input clock,sync_reset;
        input [31:0] a,b;
        input [7:0] state;
        input lohi;
        input mul_div_enable,mul_div_sign,mul_div_word,mul_div_mode;
        output stop_state;
        output [31:0] mul_div_out;
 
        reg [31:0] a_reg;
        reg [31:0] b_reg;
        reg [31:0] answer_reg;
 
        reg stop_state_reg;// For state control
        reg [5:0] counter;
        reg mul_div_sign_ff,mul_div_mode_ff;
        reg a31_latch,b31_latch;
        reg breg31;
//mult64
        wire [63:0] ab62={1'b0,a_reg[31]*breg31,62'h0};//Jul.5.2004
        wire [63:0] shift_a31=mul_div_sign_ff  ? ~{2'b0,a_reg[30:0],31'h0}+1'b1: {2'b0,a_reg[30:0],31'h0} ;//Jul.13.2004 Jul.2.2004
        wire [63:0] shift_b31=mul_div_sign_ff  ? ~{2'b0,b_reg[30:0],31'h0}+1'b1: {2'b0,b_reg[30:0],31'h0};//Jul.13.2004 Jul.2.2004
 
        wire [30:0] init_lower  =breg31*shift_a31[30:0] +a_reg[31]*shift_b31[30:0]+ab62[30:0];//Jul.5.2004
        wire [63:31] init_upper=breg31*shift_a31[63:31]+a_reg[31]*shift_b31[63:31]+ab62[63:31];//+carry;Jul.5.2004
        wire [63:0] init_val={init_upper,init_lower};
        wire [MUL_WIDTH+30    :0] mult32x4out_temp=a_reg[30:0]*b_reg[MUL_WIDTH-1:0];//Jul.5.2004           
        wire [MUL_WIDTH+31 :0] mult32x4out={1'b0,mult32x4out_temp};
      reg [63:0] mult64_reg;
        reg [31:0] multout_reg;
        wire [63:0] mult64_out;
        wire  [63:0] mult64=a_reg* b_reg;
        reg  [MUL_WIDTH+31-1+1 :0] mult32x4out_reg;
 
 
        wire finish_operation;
        wire pre_stop;
        wire [32:0] sum;
        wire [31:0] answer_inc;
        wire [31:0] aminus=-a;
        wire [31:0] div_out,div_out_tmp;
 
 
        wire mul_div_mode_w;
        reg mul_state_reg;
        reg div_msb_ff;
 
        assign mul_div_mode_w=pre_stop ? mul_div_mode: mul_div_mode_ff;
 
`ifdef RAM4K
//less area
 
        assign mul_div_out=!lohi ?  !mul_div_mode_ff ?  mult64_out[31:0] : div_out  :
                                          !mul_div_mode_ff ? mult64_out[63:32]  :       div_out;//Jul.16.2004   
 
        assign div_out_tmp=!lohi ? answer_reg: {div_msb_ff,multout_reg[31:1]};
        assign div_out= (!lohi && (a31_latch ^ b31_latch)  &&  mul_div_sign_ff) ||
                                           (lohi && mul_div_sign_ff && a31_latch) ? ~div_out_tmp+1'b1 : div_out_tmp;
 
`else
 
// faster
        reg [31:0] div_out_multout_latch,answer_reg_latch;//
 
        assign mul_div_out=!lohi ?  !mul_div_mode_ff ? mult64_out[31:0]   : answer_reg_latch  :
                                    !mul_div_mode_ff ? mult64_out[63:32]  : div_out_multout_latch;//Jul.16.2004 
 
 
 
        always @(posedge clock) begin
                if ( (a31_latch ^ b31_latch)  &&  mul_div_sign_ff)
                        answer_reg_latch<=~answer_reg+1'b1;
                else    answer_reg_latch<= answer_reg;
 
                if  ( mul_div_sign_ff && a31_latch)
                        div_out_multout_latch<=~{div_msb_ff,multout_reg[31:1]}+1'b1;
                else div_out_multout_latch<={div_msb_ff,multout_reg[31:1]};
 
 
        end
 
 
`endif
 
//mul64
        //mul_state 
        always @(posedge clock) begin
                 breg31<=b[31];
        end
        always @(posedge clock) begin
                mult32x4out_reg<=mult32x4out;
        end
 
//Jul.16.2004
        always @(posedge clock) begin
                if (sync_reset) mul_state_reg<=0;
                else if (pre_stop && mul_div_mode_w==`MUL_DIV_MUL_SEL ) mul_state_reg<=1;
                else if (finish_operation) mul_state_reg<=0;
        end
 
        //mult64_reg multout_reg
        always @(posedge clock) begin
                if (mul_state_reg && counter==0 )begin
                                mult64_reg<=init_val;//Jul.13.2004 Jul.5.2004 Jul.4.2004
                end
                else
                        if (mul_state_reg) begin
                                    {mult64_reg,multout_reg[31:31-MUL_WIDTH+1]}<={{MUL_WIDTH {1'b0}},mult64_reg+mult32x4out_reg};
                                    multout_reg[31-MUL_WIDTH:0] <=multout_reg[31:MUL_WIDTH];
 
                //Division
                end  else if (pre_stop && counter==0 ) multout_reg<=0; //First
                else if (mul_div_mode_ff && stop_state_reg ) begin
                                if (sum[32]==1'b0) begin //if (a_reg >=b_reg)
                                        if (finish_operation) div_msb_ff<=sum[31];
                                      multout_reg<={sum,a_reg[31]};
                                end else begin
                                        if (finish_operation) div_msb_ff<=multout_reg[31];
                                        multout_reg[0]<=a_reg[31];
                                        multout_reg[31:1] <=multout_reg[30:0];
                                end
                end
        end
 
        assign mult64_out={mult64_reg[31:0],multout_reg[31:0]};
//input FFs
 
        always @(posedge clock) begin
                if (sync_reset) begin
                        mul_div_sign_ff<=0;
                        mul_div_mode_ff<=0;
 
 
                end else if (pre_stop) begin
                        mul_div_sign_ff<=mul_div_sign;
                        a31_latch<=a[31];
                        b31_latch<=b[31];
                        mul_div_mode_ff<=mul_div_mode;
                end
        end
 
 
 
//state_machine
        assign pre_stop=mul_div_enable ;
        assign finish_operation=(mul_div_mode_ff && counter==32) || (mul_state_reg && counter==MUL_STATE_MSB) ;//Jul.2.2004
 
 
        always @(posedge clock) begin
                if (sync_reset) stop_state_reg <=0;
                else if (pre_stop && !stop_state_reg )  stop_state_reg<=1;
                else if (stop_state_reg && finish_operation) stop_state_reg<=0;
        end
 
        assign stop_state=stop_state_reg;
 
        always @(posedge clock) begin
                if (sync_reset) counter <=0;
                else if (!stop_state_reg) counter <=0;
                else if (stop_state_reg ) counter <=counter+1;
        end
 
//a_reg
        always @(posedge clock) begin
                if(mul_div_mode_w==`MUL_DIV_MUL_SEL && pre_stop)  a_reg <=a;//
              else if(mul_div_mode_w !=`MUL_DIV_MUL_SEL )begin//
                        if (!stop_state_reg && !pre_stop) a_reg <=a_reg;//
                        else if (pre_stop && counter==0  ) begin //
                                if (mul_div_sign) begin//
                                        if (a[31])       a_reg <=aminus;//
                                      else a_reg <=a;
                                end else  a_reg <=a;//
                        end else begin//div 
                                                 a_reg <={a_reg[30:0],1'b0};// a_reg <<=1;
                        end
 
                end
         end
 
//b_reg
        always @(posedge clock) begin
                if (pre_stop && mul_div_mode_w==`MUL_DIV_MUL_SEL )      b_reg<={1'b0,b[30:0]};
                else if ( mul_state_reg) b_reg<=b_reg[31:MUL_WIDTH];
              else if( mul_div_mode_w !=`MUL_DIV_MUL_SEL) begin//
                        if (!stop_state_reg && !pre_stop ) b_reg <=b_reg;//
                        else if (pre_stop && counter==0 ) begin //
                                if (mul_div_sign) begin//
                                        if ( b[31])  b_reg <=-b[31:0];//
                                      else  b_reg <=b[31:0];//
                                end else begin
                                        b_reg <=b[31:0];//
                                end
                        end else begin//div 
                                         b_reg <=b_reg;//;
                        end
                end
         end
 
//answer_reg
        always @(posedge clock) begin
 
              if (mul_div_mode_w !=`MUL_DIV_MUL_SEL) begin//
                        if (!stop_state_reg && !pre_stop) answer_reg <=answer_reg;//
                        else if (pre_stop && counter==0  ) answer_reg<=0; //
                        else  begin//div 
                                if ( !sum[32] ) begin//
                                         if (finish_operation) answer_reg <=answer_inc;
                                         else answer_reg <={answer_inc[30:0],1'b0};   //Jun.7.2004  a_reg -= b_reg
                                end else begin
                                         if  (finish_operation ) begin
                                                 answer_reg <=answer_reg;
                                         end else answer_reg <={answer_reg[30:0],1'b0};   // answer_reg <<=1;
                                end
                        end
                end
         end
 
 
        assign sum={1'b0,multout_reg}+~{1'b0,b_reg}+1'b1;//
 
      assign answer_inc=answer_reg+1'b1;//Jun.7.2004
 
endmodule
 

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[/] [yacc/] [trunk/] [syn/] [xilinx/] [mul_div_module5.v] - Blame information for rev 4

Line No.	Rev	Author	Line
1	2	tak.sugawa	`//Jun.2.2004`
2			`//Jun.27.2004`
3			`//Jun.28.2004`
4			`//Jun.30.2004 mulfunc output bug fix`
5			`// still 16x16 sign extension`
6			`//Jul.2.2004 mul 32x32=>64bit w/ w/o sign`
7			`//Jul.2.2004 address MUL_WIDTH==1`
8			`//Jul.4.2004 input critical path : => add carry_ff;`
9			`//Jul.5.2004 :=> less fanout`
10			`//Jul.13.2004 signed mul bug fix`
11			`//Jul.15.2004 32/32 div`
12			`//Jul.16.2004 diet`
13			//Jul.17.2004 add `ifdef less path delay for interface port
14			`//Apr.7.2005 ADDRESS to XILINX Specific problem`
15
16			`// mul/div module`
17
18			`// a[31:0] /b[31:0] =>`
19			`// mul_div_out[15:0] <=a/b`
20			`// mul_div_out[31:16] <=a%b`
21			`// No detection of overflow`
22			`// Algorithm`
23			`// answer_reg = (answer_reg << 1);`
24			`// multout_reg<={sum,a_reg[31]};`
25			`// if (multout_reg >= b_reg) {`
26			`// answer_reg += 1;`
27			`// multout_reg -= b_reg;`
28			`// }`
29			`// a_reg <= a_reg << 1;`
30			`include "define.h"
31			`module mul_div(clock,sync_reset,a,b,mul_div_out,mul_div_sign,mul_div_word,mul_div_mode,state,stop_state,mul_div_enable,lohi);`
32			`ifdef RAM4K
33
34			`ifdef XILINX
35			`parameter MUL_WIDTH=16;//Must be 2,4,8,16 2=> less area less speed 16=> greater area but faster`
36			`parameter MUL_STATE_MSB=2;//should be 32/MUL_WIDTH-1+1;`
37			`// XILINX fails using ISE7.1 if MUL_WIDTH==1,2`
38			`// if MULWIDTH==1 synthesis is possible but post synthesis simulation fails`
39			`// if MULWIDTH==2 synthesis fails;`
40			`// MUL_WIDTH==16 shows good.`
41
42			`else
43			`parameter MUL_WIDTH=1;//Must be 2,4,8,16 2=> less area less speed 16=> greater area but faster`
44			`parameter MUL_STATE_MSB=32;//should be 32/MUL_WIDTH-1+1;`
45			`endif
46			`else
47			`ifdef XILINX
48			`parameter MUL_WIDTH=16;//Must be 2,4,8,16 2=> less area less speed 16=> greater area but faster`
49			`parameter MUL_STATE_MSB=2;//should be 32/MUL_WIDTH-1+1;`
50			`// XILINX fails using ISE7.1 if MUL_WIDTH==1,2`
51			`// if MULWIDTH==1 synthesis is possible but post synthesis simulation fails`
52			`// if MULWIDTH==2 synthesis fails;`
53			`// MUL_WIDTH==16 shows good.`
54
55			`else
56			`parameter MUL_WIDTH=1;//Must be 2,4,8,16 2=> less area less speed 16=> greater area but faster`
57			`parameter MUL_STATE_MSB=32;//should be 32/MUL_WIDTH-1+1;`
58			`endif
59			`endif
60			`input clock,sync_reset;`
61			`input [31:0] a,b;`
62			`input [7:0] state;`
63			`input lohi;`
64			`input mul_div_enable,mul_div_sign,mul_div_word,mul_div_mode;`
65			`output stop_state;`
66			`output [31:0] mul_div_out;`
67
68			`reg [31:0] a_reg;`
69			`reg [31:0] b_reg;`
70			`reg [31:0] answer_reg;`
71
72			`reg stop_state_reg;// For state control`
73			`reg [5:0] counter;`
74			`reg mul_div_sign_ff,mul_div_mode_ff;`
75			`reg a31_latch,b31_latch;`
76			`reg breg31;`
77			`//mult64`
78			`wire [63:0] ab62={1'b0,a_reg[31]*breg31,62'h0};//Jul.5.2004`
79			`wire [63:0] shift_a31=mul_div_sign_ff ? ~{2'b0,a_reg[30:0],31'h0}+1'b1: {2'b0,a_reg[30:0],31'h0} ;//Jul.13.2004 Jul.2.2004`
80			`wire [63:0] shift_b31=mul_div_sign_ff ? ~{2'b0,b_reg[30:0],31'h0}+1'b1: {2'b0,b_reg[30:0],31'h0};//Jul.13.2004 Jul.2.2004`
81
82			`wire [30:0] init_lower =breg31shift_a31[30:0] +a_reg[31]shift_b31[30:0]+ab62[30:0];//Jul.5.2004`
83			`wire [63:31] init_upper=breg31shift_a31[63:31]+a_reg[31]shift_b31[63:31]+ab62[63:31];//+carry;Jul.5.2004`
84			`wire [63:0] init_val={init_upper,init_lower};`
85			`wire [MUL_WIDTH+30 :0] mult32x4out_temp=a_reg[30:0]*b_reg[MUL_WIDTH-1:0];//Jul.5.2004`
86			`wire [MUL_WIDTH+31 :0] mult32x4out={1'b0,mult32x4out_temp};`
87			`reg [63:0] mult64_reg;`
88			`reg [31:0] multout_reg;`
89			`wire [63:0] mult64_out;`
90			`wire [63:0] mult64=a_reg* b_reg;`
91			`reg [MUL_WIDTH+31-1+1 :0] mult32x4out_reg;`
92
93
94			`wire finish_operation;`
95			`wire pre_stop;`
96			`wire [32:0] sum;`
97			`wire [31:0] answer_inc;`
98			`wire [31:0] aminus=-a;`
99			`wire [31:0] div_out,div_out_tmp;`
100
101
102			`wire mul_div_mode_w;`
103			`reg mul_state_reg;`
104			`reg div_msb_ff;`
105
106			`assign mul_div_mode_w=pre_stop ? mul_div_mode: mul_div_mode_ff;`
107
108			`ifdef RAM4K
109			`//less area`
110
111			`assign mul_div_out=!lohi ? !mul_div_mode_ff ? mult64_out[31:0] : div_out :`
112			`!mul_div_mode_ff ? mult64_out[63:32] : div_out;//Jul.16.2004`
113
114			`assign div_out_tmp=!lohi ? answer_reg: {div_msb_ff,multout_reg[31:1]};`
115			`assign div_out= (!lohi && (a31_latch ^ b31_latch) && mul_div_sign_ff) \|\|`
116			`(lohi && mul_div_sign_ff && a31_latch) ? ~div_out_tmp+1'b1 : div_out_tmp;`
117
118			`else
119
120			`// faster`
121			`reg [31:0] div_out_multout_latch,answer_reg_latch;//`
122
123			`assign mul_div_out=!lohi ? !mul_div_mode_ff ? mult64_out[31:0] : answer_reg_latch :`
124			`!mul_div_mode_ff ? mult64_out[63:32] : div_out_multout_latch;//Jul.16.2004`
125
126
127
128			`always @(posedge clock) begin`
129			`if ( (a31_latch ^ b31_latch) && mul_div_sign_ff)`
130			`answer_reg_latch<=~answer_reg+1'b1;`
131			`else answer_reg_latch<= answer_reg;`
132
133			`if ( mul_div_sign_ff && a31_latch)`
134			`div_out_multout_latch<=~{div_msb_ff,multout_reg[31:1]}+1'b1;`
135			`else div_out_multout_latch<={div_msb_ff,multout_reg[31:1]};`
136
137
138			`end`
139
140
141			`endif
142
143			`//mul64`
144			`//mul_state`
145			`always @(posedge clock) begin`
146			`breg31<=b[31];`
147			`end`
148			`always @(posedge clock) begin`
149			`mult32x4out_reg<=mult32x4out;`
150			`end`
151
152			`//Jul.16.2004`
153			`always @(posedge clock) begin`
154			`if (sync_reset) mul_state_reg<=0;`
155			else if (pre_stop && mul_div_mode_w==`MUL_DIV_MUL_SEL ) mul_state_reg<=1;
156			`else if (finish_operation) mul_state_reg<=0;`
157			`end`
158
159			`//mult64_reg multout_reg`
160			`always @(posedge clock) begin`
161			`if (mul_state_reg && counter==0 )begin`
162			`mult64_reg<=init_val;//Jul.13.2004 Jul.5.2004 Jul.4.2004`
163			`end`
164			`else`
165			`if (mul_state_reg) begin`
166			`{mult64_reg,multout_reg[31:31-MUL_WIDTH+1]}<={{MUL_WIDTH {1'b0}},mult64_reg+mult32x4out_reg};`
167			`multout_reg[31-MUL_WIDTH:0] <=multout_reg[31:MUL_WIDTH];`
168
169			`//Division`
170			`end else if (pre_stop && counter==0 ) multout_reg<=0; //First`
171			`else if (mul_div_mode_ff && stop_state_reg ) begin`
172			`if (sum[32]==1'b0) begin //if (a_reg >=b_reg)`
173			`if (finish_operation) div_msb_ff<=sum[31];`
174			`multout_reg<={sum,a_reg[31]};`
175			`end else begin`
176			`if (finish_operation) div_msb_ff<=multout_reg[31];`
177			`multout_reg[0]<=a_reg[31];`
178			`multout_reg[31:1] <=multout_reg[30:0];`
179			`end`
180			`end`
181			`end`
182
183			`assign mult64_out={mult64_reg[31:0],multout_reg[31:0]};`
184			`//input FFs`
185
186			`always @(posedge clock) begin`
187			`if (sync_reset) begin`
188			`mul_div_sign_ff<=0;`
189			`mul_div_mode_ff<=0;`
190
191
192			`end else if (pre_stop) begin`
193			`mul_div_sign_ff<=mul_div_sign;`
194			`a31_latch<=a[31];`
195			`b31_latch<=b[31];`
196			`mul_div_mode_ff<=mul_div_mode;`
197			`end`
198			`end`
199
200
201
202			`//state_machine`
203			`assign pre_stop=mul_div_enable ;`
204			`assign finish_operation=(mul_div_mode_ff && counter==32) \|\| (mul_state_reg && counter==MUL_STATE_MSB) ;//Jul.2.2004`
205
206
207			`always @(posedge clock) begin`
208			`if (sync_reset) stop_state_reg <=0;`
209			`else if (pre_stop && !stop_state_reg ) stop_state_reg<=1;`
210			`else if (stop_state_reg && finish_operation) stop_state_reg<=0;`
211			`end`
212
213			`assign stop_state=stop_state_reg;`
214
215			`always @(posedge clock) begin`
216			`if (sync_reset) counter <=0;`
217			`else if (!stop_state_reg) counter <=0;`
218			`else if (stop_state_reg ) counter <=counter+1;`
219			`end`
220
221			`//a_reg`
222			`always @(posedge clock) begin`
223			if(mul_div_mode_w==`MUL_DIV_MUL_SEL && pre_stop) a_reg <=a;//
224			else if(mul_div_mode_w !=`MUL_DIV_MUL_SEL )begin//
225			`if (!stop_state_reg && !pre_stop) a_reg <=a_reg;//`
226			`else if (pre_stop && counter==0 ) begin //`
227			`if (mul_div_sign) begin//`
228			`if (a[31]) a_reg <=aminus;//`
229			`else a_reg <=a;`
230			`end else a_reg <=a;//`
231			`end else begin//div`
232			`a_reg <={a_reg[30:0],1'b0};// a_reg <<=1;`
233			`end`
234
235			`end`
236			`end`
237
238			`//b_reg`
239			`always @(posedge clock) begin`
240			if (pre_stop && mul_div_mode_w==`MUL_DIV_MUL_SEL ) b_reg<={1'b0,b[30:0]};
241			`else if ( mul_state_reg) b_reg<=b_reg[31:MUL_WIDTH];`
242			else if( mul_div_mode_w !=`MUL_DIV_MUL_SEL) begin//
243			`if (!stop_state_reg && !pre_stop ) b_reg <=b_reg;//`
244			`else if (pre_stop && counter==0 ) begin //`
245			`if (mul_div_sign) begin//`
246			`if ( b[31]) b_reg <=-b[31:0];//`
247			`else b_reg <=b[31:0];//`
248			`end else begin`
249			`b_reg <=b[31:0];//`
250			`end`
251			`end else begin//div`
252			`b_reg <=b_reg;//;`
253			`end`
254			`end`
255			`end`
256
257			`//answer_reg`
258			`always @(posedge clock) begin`
259
260			if (mul_div_mode_w !=`MUL_DIV_MUL_SEL) begin//
261			`if (!stop_state_reg && !pre_stop) answer_reg <=answer_reg;//`
262			`else if (pre_stop && counter==0 ) answer_reg<=0; //`
263			`else begin//div`
264			`if ( !sum[32] ) begin//`
265			`if (finish_operation) answer_reg <=answer_inc;`
266			`else answer_reg <={answer_inc[30:0],1'b0}; //Jun.7.2004 a_reg -= b_reg`
267			`end else begin`
268			`if (finish_operation ) begin`
269			`answer_reg <=answer_reg;`
270			`end else answer_reg <={answer_reg[30:0],1'b0}; // answer_reg <<=1;`
271			`end`
272			`end`
273			`end`
274			`end`
275
276
277			`assign sum={1'b0,multout_reg}+~{1'b0,b_reg}+1'b1;//`
278
279			`assign answer_inc=answer_reg+1'b1;//Jun.7.2004`
280
281			`endmodule`
282