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--     This file is owned and controlled by Xilinx and must be used           --

--     solely for design, simulation, implementation and creation of          --

--     design files limited to Xilinx devices or technologies. Use            --

--     with non-Xilinx devices or technologies is expressly prohibited        --

--     and immediately terminates your license.                               --

--                                                                            --

--     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"          --

--     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                --

--     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION        --

--     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION            --

--     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS              --

--     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                --

--     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE       --

--     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY               --

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--     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR         --

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--     FOR A PARTICULAR PURPOSE.                                              --

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--     expressly prohibited.                                                  --

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--     (c) Copyright 1995-2004 Xilinx, Inc.                                   --

--     All rights reserved.                                                   --

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-- The following code must appear in the VHDL architecture header:

------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG

component ram1k0

        port (

        addra: IN std_logic_VECTOR(11 downto 0);

        addrb: IN std_logic_VECTOR(11 downto 0);

        clka: IN std_logic;

        clkb: IN std_logic;

        dina: IN std_logic_VECTOR(7 downto 0);

        dinb: IN std_logic_VECTOR(7 downto 0);

        douta: OUT std_logic_VECTOR(7 downto 0);

        doutb: OUT std_logic_VECTOR(7 downto 0);

        wea: IN std_logic;

        web: IN std_logic);

end component;

-- FPGA Express Black Box declaration

attribute fpga_dont_touch: string;

attribute fpga_dont_touch of ram1k0: component is "true";

-- Synplicity black box declaration

attribute syn_black_box : boolean;

attribute syn_black_box of ram1k0: component is true;

-- COMP_TAG_END ------ End COMPONENT Declaration ------------

-- The following code must appear in the VHDL architecture

-- body. Substitute your own instance name and net names.

------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG

your_instance_name : ram1k0

                port map (

                        addra => addra,

                        addrb => addrb,

                        clka => clka,

                        clkb => clkb,

                        dina => dina,

                        dinb => dinb,

                        douta => douta,

                        doutb => doutb,

                        wea => wea,

                        web => web);

-- INST_TAG_END ------ End INSTANTIATION Template ------------

-- You must compile the wrapper file ram1k0.vhd when simulating

-- the core, ram1k0. When compiling the wrapper file, be sure to

-- reference the XilinxCoreLib VHDL simulation library. For detailed

-- instructions, please refer to the "CORE Generator Help".