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tak.sugawa |
# BEGIN Project Options
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SET flowvendor = Foundation_iSE
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SET vhdlsim = True
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SET verilogsim = True
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SET workingdirectory = F:\yacc\syn\xilinx
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SET speedgrade = -4
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SET simulationfiles = Behavioral
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SET asysymbol = True
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SET addpads = False
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# SET outputdirectory = F:\yacc\syn\xilinx
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SET device = xc3s200
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SET implementationfiletype = Edif
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SET busformat = BusFormatAngleBracketNotRipped
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SET foundationsym = False
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SET package = ft256
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SET createndf = False
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SET designentry = VHDL
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SET devicefamily = spartan3
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SET formalverification = False
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SET removerpms = False
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# END Project Options
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# BEGIN Select
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SELECT Dual_Port_Block_Memory family Xilinx,_Inc. 6.1
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# END Select
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# BEGIN Parameters
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CSET port_a_init_value=0
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CSET port_b_init_pin=false
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CSET port_b_enable_pin_polarity=Active_High
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CSET port_a_additional_output_pipe_stages=0
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CSET coefficient_file=F:\yacc\syn\xilinx\code0.coe
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CSET port_b_initialization_pin_polarity=Active_High
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CSET select_primitive=16kx1
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CSET port_a_init_pin=false
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CSET port_a_handshaking_pins=false
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CSET port_b_active_clock_edge=Rising_Edge_Triggered
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CSET global_init_value=0
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CSET port_a_enable_pin_polarity=Active_High
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CSET port_b_init_value=0
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CSET depth_a=4096
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CSET depth_b=4096
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CSET port_a_write_enable_polarity=Active_High
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CSET component_name=ram1k0
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CSET disable_warning_messages=true
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CSET write_mode_port_a=Read_After_Write
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CSET configuration_port_a=Read_And_Write
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CSET port_a_enable_pin=false
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CSET write_mode_port_b=Read_After_Write
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CSET configuration_port_b=Read_And_Write
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CSET port_b_register_inputs=false
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CSET primitive_selection=Optimize_For_Area
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CSET width_a=8
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CSET width_b=8
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CSET port_a_active_clock_edge=Rising_Edge_Triggered
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CSET port_b_additional_output_pipe_stages=0
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CSET port_b_write_enable_polarity=Active_High
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CSET load_init_file=true
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CSET port_a_register_inputs=false
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CSET port_b_handshaking_pins=false
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CSET port_a_initialization_pin_polarity=Active_High
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CSET port_b_enable_pin=false
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# END Parameters
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GENERATE
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