| 1 |
2 |
tak.sugawa |
# BEGIN Project Options
|
| 2 |
|
|
SET flowvendor = Foundation_iSE
|
| 3 |
|
|
SET vhdlsim = True
|
| 4 |
|
|
SET verilogsim = True
|
| 5 |
|
|
SET workingdirectory = F:\yacc\syn\xilinx
|
| 6 |
|
|
SET speedgrade = -4
|
| 7 |
|
|
SET simulationfiles = Behavioral
|
| 8 |
|
|
SET asysymbol = True
|
| 9 |
|
|
SET addpads = False
|
| 10 |
|
|
# SET outputdirectory = F:\yacc\syn\xilinx
|
| 11 |
|
|
SET device = xc3s200
|
| 12 |
|
|
SET implementationfiletype = Edif
|
| 13 |
|
|
SET busformat = BusFormatAngleBracketNotRipped
|
| 14 |
|
|
SET foundationsym = False
|
| 15 |
|
|
SET package = ft256
|
| 16 |
|
|
SET createndf = False
|
| 17 |
|
|
SET designentry = VHDL
|
| 18 |
|
|
SET devicefamily = spartan3
|
| 19 |
|
|
SET formalverification = False
|
| 20 |
|
|
SET removerpms = False
|
| 21 |
|
|
# END Project Options
|
| 22 |
|
|
# BEGIN Select
|
| 23 |
|
|
SELECT Dual_Port_Block_Memory family Xilinx,_Inc. 6.1
|
| 24 |
|
|
# END Select
|
| 25 |
|
|
# BEGIN Parameters
|
| 26 |
|
|
CSET port_a_init_value=0
|
| 27 |
|
|
CSET port_b_init_pin=false
|
| 28 |
|
|
CSET port_b_enable_pin_polarity=Active_High
|
| 29 |
|
|
CSET port_a_additional_output_pipe_stages=0
|
| 30 |
|
|
CSET coefficient_file=F:\yacc\syn\xilinx\code2.coe
|
| 31 |
|
|
CSET port_b_initialization_pin_polarity=Active_High
|
| 32 |
|
|
CSET select_primitive=16kx1
|
| 33 |
|
|
CSET port_a_init_pin=false
|
| 34 |
|
|
CSET port_b_active_clock_edge=Rising_Edge_Triggered
|
| 35 |
|
|
CSET port_a_handshaking_pins=false
|
| 36 |
|
|
CSET global_init_value=0
|
| 37 |
|
|
CSET port_a_enable_pin_polarity=Active_High
|
| 38 |
|
|
CSET port_b_init_value=0
|
| 39 |
|
|
CSET depth_a=4096
|
| 40 |
|
|
CSET depth_b=4096
|
| 41 |
|
|
CSET port_a_write_enable_polarity=Active_High
|
| 42 |
|
|
CSET component_name=ram1k2
|
| 43 |
|
|
CSET disable_warning_messages=true
|
| 44 |
|
|
CSET port_a_enable_pin=false
|
| 45 |
|
|
CSET configuration_port_a=Read_And_Write
|
| 46 |
|
|
CSET write_mode_port_a=Read_After_Write
|
| 47 |
|
|
CSET configuration_port_b=Read_And_Write
|
| 48 |
|
|
CSET write_mode_port_b=Read_After_Write
|
| 49 |
|
|
CSET port_b_register_inputs=false
|
| 50 |
|
|
CSET primitive_selection=Optimize_For_Area
|
| 51 |
|
|
CSET width_a=8
|
| 52 |
|
|
CSET width_b=8
|
| 53 |
|
|
CSET port_a_active_clock_edge=Rising_Edge_Triggered
|
| 54 |
|
|
CSET port_b_additional_output_pipe_stages=0
|
| 55 |
|
|
CSET port_b_write_enable_polarity=Active_High
|
| 56 |
|
|
CSET load_init_file=true
|
| 57 |
|
|
CSET port_a_register_inputs=false
|
| 58 |
|
|
CSET port_a_initialization_pin_polarity=Active_High
|
| 59 |
|
|
CSET port_b_handshaking_pins=false
|
| 60 |
|
|
CSET port_b_enable_pin=false
|
| 61 |
|
|
# END Parameters
|
| 62 |
|
|
GENERATE
|
| 63 |
|
|
|
| 64 |
|
|
|
