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[/] [yacc/] [trunk/] [syn/] [xilinx/] [ram32x32_readme.txt] - Blame information for rev 4
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tak.sugawa |
The following files were generated for in directory
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F:\yacc\syn\xilinx:
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ram32x32.asy:
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Graphical symbol information file. Used by the ISE tools and some
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third party tools to create a symbol representing the core.
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ram32x32.edn:
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Electronic Data Netlist (EDN) file containing the information
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required to implement the module in a Xilinx (R) FPGA.
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ram32x32.sym:
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Please see the core data sheet.
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ram32x32.v:
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Verilog wrapper file provided to support functional simulation.
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This file contains simulation model customization data that is
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passed to a parameterized simulation model for the core.
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ram32x32.veo:
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VEO template file containing code that can be used as a model for
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instantiating a CORE Generator module in a Verilog design.
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ram32x32.vhd:
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VHDL wrapper file provided to support functional simulation. This
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file contains simulation model customization data that is passed to
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a parameterized simulation model for the core.
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ram32x32.vho:
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VHO template file containing code that can be used as a model for
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instantiating a CORE Generator module in a VHDL design.
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ram32x32.xco:
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CORE Generator input file containing the parameters used to
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regenerate a core.
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ram32x32_flist.txt:
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Text file listing all of the output files produced when a customized
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core was generated in the CORE Generator.
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ram32x32_readme.txt:
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Text file indicating the files generated and how they are used.
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Please see the Xilinx CORE Generator online help for further details on
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generated files and how to use them.
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