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[/] [yacc/] [trunk/] [syn/] [xilinx/] [ram32x32_xilinx.versim_map] - Blame information for rev 4

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Line No. Rev Author Line
1 2 tak.sugawa
ram32x32_xilinx.versim_map -- generated only for ProjNav status tracking
2
Simulation Model Target: ModelSim SE (Verilog)

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