URL https://opencores.org/ocsvn/yacc/yacc/trunk

Subversion Repositories yacc

[/] [yacc/] [trunk/] [syn/] [xilinx/] [ram32x32_xilinx.versim_map] - Blame information for rev 4

Line No.	Rev	Author	Line
1	2	tak.sugawa	`ram32x32_xilinx.versim_map -- generated only for ProjNav status tracking`
2			`Simulation Model Target: ModelSim SE (Verilog)`