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tak.sugawa |
Release 7.1i - Bitgen H.38
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Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
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Loading device for application Rf_Device from file '3s200.nph' in environment
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E:/Xilinx7.1.
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"s3_vsmpl" is an NCD, version 3.1, device xc3s200, package ft256, speed -4
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Opened constraints file s3_vsmpl.pcf.
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WED 13 APR 22:28:51 2005
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E:/Xilinx7.1/bin/nt/bitgen.exe -intstyle ise -w -g DebugBitstream:No -g Binary:no -g CRC:Enable -g ConfigRate:6 -g CclkPin:PullUp -g M0Pin:PullUp -g M1Pin:PullUp -g M2Pin:PullUp -g ProgPin:PullUp -g DonePin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g DCIUpdateMode:AsRequired -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:No -g DriveDone:No s3_vsmpl.ncd
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Summary of Bitgen Options:
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+----------------------+----------------------+
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| Option Name | Current Setting |
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+----------------------+----------------------+
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| Compress | (Not Specified)* |
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+----------------------+----------------------+
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| Readback | (Not Specified)* |
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+----------------------+----------------------+
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| CRC | Enable** |
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+----------------------+----------------------+
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| DebugBitstream | No** |
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+----------------------+----------------------+
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| ConfigRate | 6** |
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+----------------------+----------------------+
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| StartupClk | Cclk** |
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+----------------------+----------------------+
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| DCMShutdown | Disable* |
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+----------------------+----------------------+
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| DCIUpdateMode | AsRequired** |
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+----------------------+----------------------+
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| CclkPin | Pullup** |
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+----------------------+----------------------+
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| DonePin | Pullup** |
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+----------------------+----------------------+
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| HswapenPin | Pullup* |
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+----------------------+----------------------+
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| M0Pin | Pullup** |
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+----------------------+----------------------+
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| M1Pin | Pullup** |
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+----------------------+----------------------+
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| M2Pin | Pullup** |
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+----------------------+----------------------+
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| ProgPin | Pullup** |
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+----------------------+----------------------+
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| TckPin | Pullup** |
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+----------------------+----------------------+
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| TdiPin | Pullup** |
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+----------------------+----------------------+
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| TdoPin | Pullup** |
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+----------------------+----------------------+
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| TmsPin | Pullup** |
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+----------------------+----------------------+
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| UnusedPin | Pulldown** |
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+----------------------+----------------------+
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| GWE_cycle | 6** |
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+----------------------+----------------------+
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| GTS_cycle | 5** |
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+----------------------+----------------------+
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| LCK_cycle | NoWait** |
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+----------------------+----------------------+
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| Match_cycle | Auto* |
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+----------------------+----------------------+
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| DONE_cycle | 4** |
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+----------------------+----------------------+
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| Persist | No* |
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+----------------------+----------------------+
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| DriveDone | No** |
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+----------------------+----------------------+
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| DonePipe | No** |
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+----------------------+----------------------+
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| Security | None** |
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+----------------------+----------------------+
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| UserID | 0xFFFFFFFF** |
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+----------------------+----------------------+
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| ActivateGclk | No* |
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+----------------------+----------------------+
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| ActiveReconfig | No* |
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+----------------------+----------------------+
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| PartialMask0 | (Not Specified)* |
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+----------------------+----------------------+
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| PartialMask1 | (Not Specified)* |
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+----------------------+----------------------+
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| PartialMask2 | (Not Specified)* |
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+----------------------+----------------------+
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| PartialGclk | (Not Specified)* |
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+----------------------+----------------------+
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| PartialLeft | (Not Specified)* |
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+----------------------+----------------------+
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| PartialRight | (Not Specified)* |
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+----------------------+----------------------+
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| IEEE1532 | No* |
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+----------------------+----------------------+
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| Binary | No** |
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+----------------------+----------------------+
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* Default setting.
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** The specified setting matches the default setting.
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Running DRC.
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WARNING:PhysDesignRules:367 - The signal _IBUF> is incomplete. The
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signal does not drive any load pins in the design.
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WARNING:PhysDesignRules:367 - The signal _IBUF> is incomplete. The
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signal does not drive any load pins in the design.
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WARNING:PhysDesignRules:367 - The signal _IBUF> is incomplete. The
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signal does not drive any load pins in the design.
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WARNING:PhysDesignRules:367 - The signal is incomplete. The
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signal does not drive any load pins in the design.
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WARNING:PhysDesignRules:367 - The signal is incomplete. The
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signal does not drive any load pins in the design.
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DRC detected 0 errors and 5 warnings.
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Creating bit map...
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Saving bit stream in "s3_vsmpl.bit".
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Bitstream generation is complete.
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