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tak.sugawa |
Release 7.1i par H.38
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Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
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ATHRON:: Wed Apr 13 22:25:08 2005
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par -w -intstyle ise -ol std -t 1 s3_vsmpl_map.ncd s3_vsmpl.ncd s3_vsmpl.pcf
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Constraints file: s3_vsmpl.pcf.
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Loading device for application Rf_Device from file '3s200.nph' in environment
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E:/Xilinx7.1.
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"s3_vsmpl" is an NCD, version 3.1, device xc3s200, package ft256, speed -4
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Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
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Celsius)
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Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
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Device speed data version: "PRODUCTION 1.35 2005-01-22".
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Device Utilization Summary:
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Number of BUFGMUXs 2 out of 8 25%
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Number of External IOBs 103 out of 173 59%
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Number of LOCed IOBs 103 out of 103 100%
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Number of MULT18X18s 2 out of 12 16%
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Number of RAMB16s 11 out of 12 91%
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Number of Slices 1918 out of 1920 99%
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Number of SLICEMs 1 out of 960 1%
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Overall effort level (-ol): Standard (set by user)
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Placer effort level (-pl): Standard (set by user)
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Placer cost table entry (-t): 1
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Router effort level (-rl): Standard (set by user)
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WARNING:Par:276 - The signal button<0>_IBUF has no load
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WARNING:Par:276 - The signal button<1>_IBUF has no load
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WARNING:Par:276 - The signal button<2>_IBUF has no load
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WARNING:Par:276 - The signal PS2_DATA_IBUF has no load
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WARNING:Par:276 - The signal PS2_CLK_IBUF has no load
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Starting Placer
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Phase 1.1
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Phase 1.1 (Checksum:99018f) REAL time: 5 secs
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Phase 2.31
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Phase 2.31 (Checksum:1312cfe) REAL time: 5 secs
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Phase 3.2
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.
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Phase 3.2 (Checksum:1c9c37d) REAL time: 6 secs
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Phase 4.8
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..................................................
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Phase 4.8 (Checksum:1108dd3) REAL time: 20 secs
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Phase 5.5
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Phase 5.5 (Checksum:2faf07b) REAL time: 21 secs
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Phase 6.18
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Phase 6.18 (Checksum:39386fa) REAL time: 29 secs
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Phase 7.5
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Phase 7.5 (Checksum:42c1d79) REAL time: 29 secs
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Writing design to file s3_vsmpl.ncd
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Total REAL time to Placer completion: 31 secs
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Total CPU time to Placer completion: 24 secs
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Starting Router
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Phase 1: 13709 unrouted; REAL time: 31 secs
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Phase 2: 12745 unrouted; REAL time: 32 secs
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Phase 3: 11145 unrouted; REAL time: 36 secs
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Phase 4: 0 unrouted; REAL time: 3 mins 13 secs
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WARNING:CLK Net:clk25M<0>
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may have excessive skew because 1 NON-CLK pins
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failed to route using a CLK template.
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Total REAL time to Router completion: 3 mins 13 secs
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Total CPU time to Router completion: 2 mins 57 secs
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Generating "PAR" statistics.
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**************************
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Generating Clock Report
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**************************
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+---------------------+--------------+------+------+------------+-------------+
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| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
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+---------------------+--------------+------+------+------------+-------------+
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| clk25M<0> | BUFGMUX7| No | 804 | 0.041 | 1.052 |
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+---------------------+--------------+------+------+------------+-------------+
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| clk_BUFGP | BUFGMUX0| No | 3 | 0.040 | 1.050 |
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+---------------------+--------------+------+------+------------+-------------+
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INFO:Par:340 -
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The Delay report will not be generated when running non-timing driven PAR
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with effort level Standard or Medium. If a delay report is required please do
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one of the following: 1) use effort level High, 2) use the following
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environment variable "XIL_PAR_GENERATE_DLY_REPORT", 3) create Timing
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constraints for the design.
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Generating Pad Report.
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All signals are completely routed.
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Total REAL time to PAR completion: 3 mins 18 secs
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Total CPU time to PAR completion: 3 mins
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Peak Memory Usage: 104 MB
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Placement: Completed - No errors found.
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Routing: Completed - No errors found.
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Number of error messages: 0
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Number of warning messages: 5
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Number of info messages: 1
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Writing design to file s3_vsmpl.ncd
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PAR done!
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