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[/] [yacc/] [trunk/] [syn/] [xilinx/] [s3_vsmpl.versim_synth] - Blame information for rev 4

Line No.	Rev	Author	Line
1	2	tak.sugawa	`s3_vsmpl.versim_synth -- generated only for ProjNav status tracking`
2			`Simulation Model Target: ModelSim SE (Verilog)`