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tak.sugawa |
Release 7.1i - netgen H.38
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Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
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Command Line: netgen -intstyle ise -s 4 -pcf yacc.pcf -sdf_anno true -w -ofmt
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verilog -sim yacc.ncd yacc_timesim.v
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Read and Annotate design 'yacc.ncd' ...
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Loading device for application Rf_Device from file '3s200.nph' in environment
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E:/Xilinx7.1.
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"yacc" is an NCD, version 3.1, device xc3s200, package ft256, speed -4
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Loading constraints from 'yacc.pcf'...
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The speed grade (-4) differs from the speed grade specified in the .ncd file
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(-4).
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The number of routable networks is 3924
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Flattening design ...
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Processing design ...
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Preping design's networks ...
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Preping design's macros ...
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Writing Verilog SDF file 'yacc_timesim.sdf' ...
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Writing Verilog netlist file 'yacc_timesim.v' ...
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INFO:NetListWriters:633 - The generated Verilog netlist contains Xilinx SIMPRIM
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simulation primitives and has to be used with SIMPRIM simulation library for
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correct compilation and simulation.
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INFO:NetListWriters:580 - If Verilog simulation is performed outside the ISE
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Project Navigator environment, please add $XILINX/verilog/src/glbl.v to the
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simulator compile and invocation commands in order to allow proper
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initialization of the design. If simulation is performed within Project
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Navigator, this will be taken care of automatically. For more information on
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compiling and performing Xilinx simulation, consult the online Synthesis and
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Verification Design Guide:
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http://support.xilinx.com/support/software_manuals.htm
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Number of warnings: 0
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Number of info messages: 2
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Total memory usage is 124760 kilobytes
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