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[/] [yavga/] [trunk/] [vhdl/] [chars_RAM.vhd] - Blame information for rev 2

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Line No. Rev Author Line
1 2 sandroamt 
--------------------------------------------------------------------------------
2 
----                                                                        ----
3 
---- This file is part of the yaVGA project                                 ----
4 
---- http://www.opencores.org/?do=project&who=yavga                         ----
5 
----                                                                        ----
6 
---- Description                                                            ----
7 
---- Implementation of yaVGA IP core                                        ----
8 
----                                                                        ----
9 
---- To Do:                                                                 ----
10 
----                                                                        ----
11 
----                                                                        ----
12 
---- Author(s):                                                             ----
13 
---- Sandro Amato, sdroamt@netscape.net                                     ----
14 
----                                                                        ----
15 
--------------------------------------------------------------------------------
16 
----                                                                        ----
17 
---- Copyright (c) 2009, Sandro Amato                                       ----
18 
---- All rights reserved.                                                   ----
19 
----                                                                        ----
20 
---- Redistribution  and  use in  source  and binary forms, with or without ----
21 
---- modification,  are  permitted  provided that  the following conditions ----
22 
---- are met:                                                               ----
23 
----                                                                        ----
24 
----     * Redistributions  of  source  code  must  retain the above        ----
25 
----       copyright   notice,  this  list  of  conditions  and  the        ----
26 
----       following disclaimer.                                            ----
27 
----     * Redistributions  in  binary form must reproduce the above        ----
28 
----       copyright   notice,  this  list  of  conditions  and  the        ----
29 
----       following  disclaimer in  the documentation and/or  other        ----
30 
----       materials provided with the distribution.                        ----
31 
----     * Neither  the  name  of  SANDRO AMATO nor the names of its        ----
32 
----       contributors may be used to  endorse or  promote products        ----
33 
----       derived from this software without specific prior written        ----
34 
----       permission.                                                      ----
35 
----                                                                        ----
36 
---- THIS SOFTWARE IS PROVIDED  BY THE COPYRIGHT  HOLDERS AND  CONTRIBUTORS ----
37 
---- "AS IS"  AND  ANY EXPRESS OR  IMPLIED  WARRANTIES, INCLUDING,  BUT NOT ----
38 
---- LIMITED  TO, THE  IMPLIED  WARRANTIES  OF MERCHANTABILITY  AND FITNESS ----
39 
---- FOR  A PARTICULAR  PURPOSE  ARE  DISCLAIMED. IN  NO  EVENT  SHALL  THE ----
40 
---- COPYRIGHT  OWNER  OR CONTRIBUTORS  BE LIABLE FOR ANY DIRECT, INDIRECT, ----
41 
---- INCIDENTAL,  SPECIAL,  EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, ----
42 
---- BUT  NOT LIMITED  TO,  PROCUREMENT OF  SUBSTITUTE  GOODS  OR SERVICES; ----
43 
---- LOSS  OF  USE,  DATA,  OR PROFITS;  OR  BUSINESS INTERRUPTION) HOWEVER ----
44 
---- CAUSED  AND  ON  ANY THEORY  OF LIABILITY, WHETHER IN CONTRACT, STRICT ----
45 
---- LIABILITY,  OR  TORT  (INCLUDING  NEGLIGENCE  OR OTHERWISE) ARISING IN ----
46 
---- ANY  WAY OUT  OF THE  USE  OF  THIS  SOFTWARE,  EVEN IF ADVISED OF THE ----
47 
---- POSSIBILITY OF SUCH DAMAGE.                                            ----
48 
--------------------------------------------------------------------------------
49 
 
50 
 
51 
library IEEE;
52 
use IEEE.STD_LOGIC_1164.all;
53 
use IEEE.STD_LOGIC_ARITH.all;
54 
use IEEE.STD_LOGIC_UNSIGNED.all;
55 
 
56 
-- Uncomment the following lines to use the declarations that are
57 
-- provided for instantiating Xilinx primitive components.
58 
library UNISIM;
59 
use UNISIM.VComponents.all;
60 
 
61 
entity chars_RAM is
62 
  port (
63 
    i_clock_rw : in  std_logic;         -- Write Clock
64 
    i_EN_rw    : in  std_logic;         -- Write RAM Enable Input
65 
    i_WE_rw    : in  std_logic_vector(3 downto 0);   -- Write Enable Input
66 
    i_ADDR_rw  : in  std_logic_vector(10 downto 0);  -- Write 11-bit Address Input
67 
    i_DI_rw    : in  std_logic_vector(31 downto 0);  -- Write 32-bit Data Input
68 
    o_DI_rw    : out std_logic_vector(31 downto 0);  -- Write 32-bit Data Input
69 
 
70 
    i_SSR : in std_logic;               -- Synchronous Set/Reset Input
71 
 
72 
    i_clock_r : in  std_logic;          -- Read Clock
73 
    i_ADDR_r  : in  std_logic_vector(12 downto 0);  -- Read 13-bit Address Input
74 
    o_DO_r    : out std_logic_vector(7 downto 0)    -- Read 8-bit Data Output
75 
    );
76 
end chars_RAM;
77 
 
78 
architecture rtl of chars_RAM is
79 
  signal s0_DO_r : std_logic_vector(7 downto 0);
80 
  signal s1_DO_r : std_logic_vector(7 downto 0);
81 
  signal s2_DO_r : std_logic_vector(7 downto 0);
82 
  signal s3_DO_r : std_logic_vector(7 downto 0);
83 
 
84 
begin
85 
 
86 
  u0_chars_ram : RAMB16_S9_S9
87 
    generic map (
88 
      WRITE_MODE_A => "WRITE_FIRST",   --  WRITE_FIRST, READ_FIRST or NO_CHANGE
89 
      INIT_A       => B"000000000",  --  Value of output RAM registers at startup
90 
      SRVAL_A      => B"000000000",     --  Ouput value upon SSR assertion
91 
      WRITE_MODE_B => "WRITE_FIRST",   --  WRITE_FIRST, READ_FIRST or NO_CHANGE
92 
      INIT_B       => B"000000000",  --  Value of output RAM registers at startup
93 
      SRVAL_B      => B"000000000",     --  Ouput value upon SSR assertion
94 
      --
95 
      INIT_00      => X"0000000000000000000000000000000000000000000000000000000000000000",
96 
      INIT_01      => X"0000000000000000000000000000000000000000000000000000000000000000",
97 
      INIT_02      => X"0000000000000000000000000000000000000000000000000000000000000000",
98 
      INIT_03      => X"0000000000000000000000000000000000000000000000000000000000000000",
99 
      INIT_04      => X"0000000000000000000000000000000000000000000000000000000000000000",
100 
      INIT_05      => X"0000000000000000000000000000000000000000000000000000000000000000",
101 
      INIT_06      => X"0000000000000000000000000000000000000000000000000000000000000000",
102 
      INIT_07      => X"0000000000000000000000000000000000000000000000000000000000000000",
103 
      INIT_08      => X"0000000000000000000000000000000000000000000000000000000000000000",
104 
      INIT_09      => X"0000000000000000000000000000000000000000000000000000000000000000",
105 
      INIT_0A      => X"0000000000000000000000000000000000000000000000000000000000000000",
106 
      INIT_0B      => X"0000000000000000000000000000000000000000000000000000000000000000",
107 
      INIT_0C      => X"0000000000000000000000000000000000000000000000000000000000000000",
108 
      INIT_0D      => X"0000000000000000000000000000000000000000000000000000000000000000",
109 
      INIT_0E      => X"0000000000000000000000000000000000000000000000000000000000000000",
110 
      INIT_0F      => X"0000000000000000000000000000000000000000000000000000000000000000",
111 
      INIT_10      => X"0000000000000000000000000000000000000000000000000000000000000000",
112 
      INIT_11      => X"0000000000000000000000000000000000000000000000000000000000000000",
113 
      INIT_12      => X"0000000000000000000000000000000000000000000000000000000000000000",
114 
      INIT_13      => X"0000000000000000000000000000000000000000000000000000000000000000",
115 
      INIT_14      => X"0000000000000000000000000000000000000000000000000000000000000000",
116 
      INIT_15      => X"0000000000000000000000000000000000000000000000000000000000000000",
117 
      INIT_16      => X"0000000000000000000000000000000000000000000000000000000000000000",
118 
      INIT_17      => X"0000000000000000000000000000000000000000000000000000000000000000",
119 
      INIT_18      => X"0000000000000000000000000000000000000000000000000000000000000000",
120 
      INIT_19      => X"0000000000000000000000000000000000000000000000000000000000000000",
121 
      INIT_1A      => X"0000000000000000000000000000000000000000000000000000000000000000",
122 
      INIT_1B      => X"0000000000000000000000000000000000000000000000000000000000000000",
123 
      INIT_1C      => X"0000000000000000000000000000000000000000000000000000000000000000",
124 
      INIT_1D      => X"0000000000000000000000000000000000000000000000000000000000000000",
125 
      INIT_1E      => X"0000000000000000000000000000000000000000000000000000000000000000",
126 
      INIT_1F      => X"0000000000000000000000000000000000000000000000000000000000000000",
127 
      INIT_20      => X"0000000000000000000000000000000000000000000000000000000000000000",
128 
      INIT_21      => X"0000000000000000000000000000000000000000000000000000000000000000",
129 
      INIT_22      => X"0000000000000000000000000000000000000000000000000000000000000000",
130 
      INIT_23      => X"0000000000000000000000000000000000000000000000000000000000000000",
131 
      INIT_24      => X"0000000000000000000000000000000000000000000000000000000000000000",
132 
      INIT_25      => X"0000000000000000000000000000000000000000000000000000000000000000",
133 
      INIT_26      => X"0000000000000000000000000000000000000000000000000000000000000000",
134 
      INIT_27      => X"0000000000000000000000000000000000000000000000000000000000000000",
135 
      INIT_28      => X"0000000000000000000000000000000000000000000000000000000000000000",
136 
      INIT_29      => X"0000000000000000000000000000000000000000000000000000000000000000",
137 
      INIT_2A      => X"0000000000000000000000000000000000000000000000000000000000000000",
138 
      INIT_2B      => X"0000000000000000000000000000000000000000000000000000000000000000",
139 
      INIT_2C      => X"0000000000000000000000000000000000000000000000000000000000000000",
140 
      INIT_2D      => X"0000000000000000000000000000000000000000000000000000000000000000",
141 
      INIT_2E      => X"0000000000000000000000000000000000000000000000000000000000000000",
142 
      INIT_2F      => X"0000000000000000000000000000000000000000000000000000000000000000",
143 
      INIT_30      => X"0000000000000000000000000000000000000000000000000000000000000000",
144 
      INIT_31      => X"0000000000000000000000000000000000000000000000000000000000000000",
145 
      INIT_32      => X"0000000000000000000000000000000000000000000000000000000000000000",
146 
      INIT_33      => X"0000000000000000000000000000000000000000000000000000000000000000",
147 
      INIT_34      => X"0000000000000000000000000000000000000000000000000000000000000000",
148 
      INIT_35      => X"0000000000000000000000000000000000000000000000000000000000000000",
149 
      INIT_36      => X"0000000000000000000000000000000000000000000000000000000000000000",
150 
      INIT_37      => X"0000000000000000000000000000000000000000000000000000000000000000",
151 
      INIT_38      => X"0000000000000000000000000000000000000000000000000000000000000000",
152 
      INIT_39      => X"0000000000000000000000000000000000000000000000000000000000000000",
153 
      INIT_3A      => X"0000000000000000000000000000000000000000000000000000000000000000",
154 
      INIT_3B      => X"0000000000000000000000000000000000000000000000000000000000000000",
155 
      INIT_3C      => X"0000000000000000000000000000000000000000000000000000000000000000",
156 
      INIT_3D      => X"0000000000000000000000000000000000000000000000000000000000000000",
157 
      INIT_3E      => X"0000000000000000000000000000000000000000000000000000000000000000",
158 
      INIT_3F      => X"0000000000000000000000000000000000000000000000000000000000000000"
159 
      )
160 
    port map(
161 
      -- read
162 
      DIA   => (others => '0'),         -- 2-bit Data Input
163 
      DIPA  => (others => '0'),
164 
      ENA   => '1',                     -- RAM Enable Input
165 
      WEA   => '0',                     -- Write Enable Input
166 
      SSRA  => i_SSR,                   -- Synchronous Set/Reset Input
167 
      CLKA  => i_clock_r,               -- Clock
168 
      ADDRA => i_ADDR_r(12 downto 2),   -- 11-bit Address Input
169 
      DOA   => s0_DO_r,                 -- 8-bit Data Output
170 
      DOPA  => open,
171 
 
172 
      -- read/write
173 
      DIB   => i_DI_rw(7 downto 0),     -- 8-bit Data Input
174 
      DIPB  => (others => '0'),
175 
      ENB   => i_EN_rw,                 -- RAM Enable Input
176 
      WEB   => i_WE_rw(0),              -- Write Enable Input
177 
      SSRB  => i_SSR,                   -- Synchronous Set/Reset Input
178 
      CLKB  => i_clock_rw,              -- Clock
179 
      ADDRB => i_ADDR_rw,               -- 11-bit Address Input
180 
      DOB   => o_DI_rw(7 downto 0),     -- 8-bit Data Input
181 
      DOPB  => open
182 
      );
183 
 
184 
  u1_chars_ram : RAMB16_S9_S9
185 
    generic map (
186 
      WRITE_MODE_A => "WRITE_FIRST",   --  WRITE_FIRST, READ_FIRST or NO_CHANGE
187 
      INIT_A       => B"000000000",  --  Value of output RAM registers at startup
188 
      SRVAL_A      => B"000000000",     --  Ouput value upon SSR assertion
189 
      WRITE_MODE_B => "WRITE_FIRST",   --  WRITE_FIRST, READ_FIRST or NO_CHANGE
190 
      INIT_B       => B"000000000",  --  Value of output RAM registers at startup
191 
      SRVAL_B      => B"000000000",     --  Ouput value upon SSR assertion
192 
      --
193 
      INIT_00      => X"0000000000000000000000000000000000000000000000000000000000000000",
194 
      INIT_01      => X"0000000000000000000000000000000000000000000000000000000000000000",
195 
      INIT_02      => X"0000000000000000000000000000000000000000000000000000000000000000",
196 
      INIT_03      => X"0000000000000000000000000000000000000000000000000000000000000000",
197 
      INIT_04      => X"0000000000000000000000000000000000000000000000000000000000000000",
198 
      INIT_05      => X"0000000000000000000000000000000000000000000000000000000000000000",
199 
      INIT_06      => X"0000000000000000000000000000000000000000000000000000000000000000",
200 
      INIT_07      => X"0000000000000000000000000000000000000000000000000000000000000000",
201 
      INIT_08      => X"0000000000000000000000000000000000000000000000000000000000000000",
202 
      INIT_09      => X"0000000000000000000000000000000000000000000000000000000000000000",
203 
      INIT_0A      => X"0000000000000000000000000000000000000000000000000000000000000000",
204 
      INIT_0B      => X"0000000000000000000000000000000000000000000000000000000000000000",
205 
      INIT_0C      => X"0000000000000000000000000000000000000000000000000000000000000000",
206 
      INIT_0D      => X"0000000000000000000000000000000000000000000000000000000000000000",
207 
      INIT_0E      => X"0000000000000000000000000000000000000000000000000000000000000000",
208 
      INIT_0F      => X"0000000000000000000000000000000000000000000000000000000000000000",
209 
      INIT_10      => X"0000000000000000000000000000000000000000000000000000000000000000",
210 
      INIT_11      => X"0000000000000000000000000000000000000000000000000000000000000000",
211 
      INIT_12      => X"0000000000000000000000000000000000000000000000000000000000000000",
212 
      INIT_13      => X"0000000000000000000000000000000000000000000000000000000000000000",
213 
      INIT_14      => X"0000000000000000000000000000000000000000000000000000000000000000",
214 
      INIT_15      => X"0000000000000000000000000000000000000000000000000000000000000000",
215 
      INIT_16      => X"0000000000000000000000000000000000000000000000000000000000000000",
216 
      INIT_17      => X"0000000000000000000000000000000000000000000000000000000000000000",
217 
      INIT_18      => X"0000000000000000000000000000000000000000000000000000000000000000",
218 
      INIT_19      => X"0000000000000000000000000000000000000000000000000000000000000000",
219 
      INIT_1A      => X"0000000000000000000000000000000000000000000000000000000000000000",
220 
      INIT_1B      => X"0000000000000000000000000000000000000000000000000000000000000000",
221 
      INIT_1C      => X"0000000000000000000000000000000000000000000000000000000000000000",
222 
      INIT_1D      => X"0000000000000000000000000000000000000000000000000000000000000000",
223 
      INIT_1E      => X"0000000000000000000000000000000000000000000000000000000000000000",
224 
      INIT_1F      => X"0000000000000000000000000000000000000000000000000000000000000000",
225 
      INIT_20      => X"0000000000000000000000000000000000000000000000000000000000000000",
226 
      INIT_21      => X"0000000000000000000000000000000000000000000000000000000000000000",
227 
      INIT_22      => X"0000000000000000000000000000000000000000000000000000000000000000",
228 
      INIT_23      => X"0000000000000000000000000000000000000000000000000000000000000000",
229 
      INIT_24      => X"0000000000000000000000000000000000000000000000000000000000000000",
230 
      INIT_25      => X"0000000000000000000000000000000000000000000000000000000000000000",
231 
      INIT_26      => X"0000000000000000000000000000000000000000000000000000000000000000",
232 
      INIT_27      => X"0000000000000000000000000000000000000000000000000000000000000000",
233 
      INIT_28      => X"0000000000000000000000000000000000000000000000000000000000000000",
234 
      INIT_29      => X"0000000000000000000000000000000000000000000000000000000000000000",
235 
      INIT_2A      => X"0000000000000000000000000000000000000000000000000000000000000000",
236 
      INIT_2B      => X"0000000000000000000000000000000000000000000000000000000000000000",
237 
      INIT_2C      => X"0000000000000000000000000000000000000000000000000000000000000000",
238 
      INIT_2D      => X"0000000000000000000000000000000000000000000000000000000000000000",
239 
      INIT_2E      => X"0000000000000000000000000000000000000000000000000000000000000000",
240 
      INIT_2F      => X"0000000000000000000000000000000000000000000000000000000000000000",
241 
      INIT_30      => X"0000000000000000000000000000000000000000000000000000000000000000",
242 
      INIT_31      => X"0000000000000000000000000000000000000000000000000000000000000000",
243 
      INIT_32      => X"0000000000000000000000000000000000000000000000000000000000000000",
244 
      INIT_33      => X"0000000000000000000000000000000000000000000000000000000000000000",
245 
      INIT_34      => X"0000000000000000000000000000000000000000000000000000000000000000",
246 
      INIT_35      => X"0000000000000000000000000000000000000000000000000000000000000000",
247 
      INIT_36      => X"0000000000000000000000000000000000000000000000000000000000000000",
248 
      INIT_37      => X"0000000000000000000000000000000000000000000000000000000000000000",
249 
      INIT_38      => X"0000000000000000000000000000000000000000000000000000000000000000",
250 
      INIT_39      => X"0000000000000000000000000000000000000000000000000000000000000000",
251 
      INIT_3A      => X"0000000000000000000000000000000000000000000000000000000000000000",
252 
      INIT_3B      => X"0000000000000000000000000000000000000000000000000000000000000000",
253 
      INIT_3C      => X"0000000000000000000000000000000000000000000000000000000000000000",
254 
      INIT_3D      => X"0000000000000000000000000000000000000000000000000000000000000000",
255 
      INIT_3E      => X"0000000000000000000000000000000000000000000000000000000000000000",
256 
      INIT_3F      => X"0000000000000000000000000000000000000000000000000000000000000000"
257 
      )
258 
    port map(
259 
      -- read
260 
      DIA   => (others => '0'),         -- 2-bit Data Input
261 
      DIPA  => (others => '0'),
262 
      ENA   => '1',                     -- RAM Enable Input
263 
      WEA   => '0',                     -- Write Enable Input
264 
      SSRA  => i_SSR,                   -- Synchronous Set/Reset Input
265 
      CLKA  => i_clock_r,               -- Clock
266 
      ADDRA => i_ADDR_r(12 downto 2),   -- 11-bit Address Input
267 
      DOA   => s1_DO_r,                 -- 8-bit Data Output
268 
      DOPA  => open,
269 
 
270 
      -- read/write
271 
      DIB   => i_DI_rw(15 downto 8),    -- 8-bit Data Input
272 
      DIPB  => (others => '0'),
273 
      ENB   => i_EN_rw,                 -- RAM Enable Input
274 
      WEB   => i_WE_rw(1),              -- Write Enable Input
275 
      SSRB  => i_SSR,                   -- Synchronous Set/Reset Input
276 
      CLKB  => i_clock_rw,              -- Clock
277 
      ADDRB => i_ADDR_rw,               -- 11-bit Address Input
278 
      DOB   => o_DI_rw(15 downto 8),    -- 8-bit Data Input
279 
      DOPB  => open
280 
      );
281 
 
282 
  u2_chars_ram : RAMB16_S9_S9
283 
    generic map (
284 
      WRITE_MODE_A => "WRITE_FIRST",   --  WRITE_FIRST, READ_FIRST or NO_CHANGE
285 
      INIT_A       => B"000000000",  --  Value of output RAM registers at startup
286 
      SRVAL_A      => B"000000000",     --  Ouput value upon SSR assertion
287 
      WRITE_MODE_B => "WRITE_FIRST",   --  WRITE_FIRST, READ_FIRST or NO_CHANGE
288 
      INIT_B       => B"000000000",  --  Value of output RAM registers at startup
289 
      SRVAL_B      => B"000000000",     --  Ouput value upon SSR assertion
290 
      --
291 
      INIT_00      => X"0000000000000000000000000000000000000000000000000000000000000000",
292 
      INIT_01      => X"0000000000000000000000000000000000000000000000000000000000000000",
293 
      INIT_02      => X"0000000000000000000000000000000000000000000000000000000000000000",
294 
      INIT_03      => X"0000000000000000000000000000000000000000000000000000000000000000",
295 
      INIT_04      => X"0000000000000000000000000000000000000000000000000000000000000000",
296 
      INIT_05      => X"0000000000000000000000000000000000000000000000000000000000000000",
297 
      INIT_06      => X"0000000000000000000000000000000000000000000000000000000000000000",
298 
      INIT_07      => X"0000000000000000000000000000000000000000000000000000000000000000",
299 
      INIT_08      => X"0000000000000000000000000000000000000000000000000000000000000000",
300 
      INIT_09      => X"0000000000000000000000000000000000000000000000000000000000000000",
301 
      INIT_0A      => X"0000000000000000000000000000000000000000000000000000000000000000",
302 
      INIT_0B      => X"0000000000000000000000000000000000000000000000000000000000000000",
303 
      INIT_0C      => X"0000000000000000000000000000000000000000000000000000000000000000",
304 
      INIT_0D      => X"0000000000000000000000000000000000000000000000000000000000000000",
305 
      INIT_0E      => X"0000000000000000000000000000000000000000000000000000000000000000",
306 
      INIT_0F      => X"0000000000000000000000000000000000000000000000000000000000000000",
307 
      INIT_10      => X"0000000000000000000000000000000000000000000000000000000000000000",
308 
      INIT_11      => X"0000000000000000000000000000000000000000000000000000000000000000",
309 
      INIT_12      => X"0000000000000000000000000000000000000000000000000000000000000000",
310 
      INIT_13      => X"0000000000000000000000000000000000000000000000000000000000000000",
311 
      INIT_14      => X"0000000000000000000000000000000000000000000000000000000000000000",
312 
      INIT_15      => X"0000000000000000000000000000000000000000000000000000000000000000",
313 
      INIT_16      => X"0000000000000000000000000000000000000000000000000000000000000000",
314 
      INIT_17      => X"0000000000000000000000000000000000000000000000000000000000000000",
315 
      INIT_18      => X"0000000000000000000000000000000000000000000000000000000000000000",
316 
      INIT_19      => X"0000000000000000000000000000000000000000000000000000000000000000",
317 
      INIT_1A      => X"0000000000000000000000000000000000000000000000000000000000000000",
318 
      INIT_1B      => X"0000000000000000000000000000000000000000000000000000000000000000",
319 
      INIT_1C      => X"0000000000000000000000000000000000000000000000000000000000000000",
320 
      INIT_1D      => X"0000000000000000000000000000000000000000000000000000000000000000",
321 
      INIT_1E      => X"0000000000000000000000000000000000000000000000000000000000000000",
322 
      INIT_1F      => X"0000000000000000000000000000000000000000000000000000000000000000",
323 
      INIT_20      => X"0000000000000000000000000000000000000000000000000000000000000000",
324 
      INIT_21      => X"0000000000000000000000000000000000000000000000000000000000000000",
325 
      INIT_22      => X"0000000000000000000000000000000000000000000000000000000000000000",
326 
      INIT_23      => X"0000000000000000000000000000000000000000000000000000000000000000",
327 
      INIT_24      => X"0000000000000000000000000000000000000000000000000000000000000000",
328 
      INIT_25      => X"0000000000000000000000000000000000000000000000000000000000000000",
329 
      INIT_26      => X"0000000000000000000000000000000000000000000000000000000000000000",
330 
      INIT_27      => X"0000000000000000000000000000000000000000000000000000000000000000",
331 
      INIT_28      => X"0000000000000000000000000000000000000000000000000000000000000000",
332 
      INIT_29      => X"0000000000000000000000000000000000000000000000000000000000000000",
333 
      INIT_2A      => X"0000000000000000000000000000000000000000000000000000000000000000",
334 
      INIT_2B      => X"0000000000000000000000000000000000000000000000000000000000000000",
335 
      INIT_2C      => X"0000000000000000000000000000000000000000000000000000000000000000",
336 
      INIT_2D      => X"0000000000000000000000000000000000000000000000000000000000000000",
337 
      INIT_2E      => X"0000000000000000000000000000000000000000000000000000000000000000",
338 
      INIT_2F      => X"0000000000000000000000000000000000000000000000000000000000000000",
339 
      INIT_30      => X"0000000000000000000000000000000000000000000000000000000000000000",
340 
      INIT_31      => X"0000000000000000000000000000000000000000000000000000000000000000",
341 
      INIT_32      => X"0000000000000000000000000000000000000000000000000000000000000000",
342 
      INIT_33      => X"0000000000000000000000000000000000000000000000000000000000000000",
343 
      INIT_34      => X"0000000000000000000000000000000000000000000000000000000000000000",
344 
      INIT_35      => X"0000000000000000000000000000000000000000000000000000000000000000",
345 
      INIT_36      => X"0000000000000000000000000000000000000000000000000000000000000000",
346 
      INIT_37      => X"0000000000000000000000000000000000000000000000000000000000000000",
347 
      INIT_38      => X"0000000000000000000000000000000000000000000000000000000000000000",
348 
      INIT_39      => X"0000000000000000000000000000000000000000000000000000000000000000",
349 
      INIT_3A      => X"0000000000000000000000000000000000000000000000000000000000000000",
350 
      INIT_3B      => X"0000000000000000000000000000000000000000000000000000000000000000",
351 
      INIT_3C      => X"0000000000000000000000000000000000000000000000000000000000000000",
352 
      INIT_3D      => X"0000000000000000000000000000000000000000000000000000000000000000",
353 
      INIT_3E      => X"0000000000000000000000000000000000000000000000000000000000000000",
354 
      INIT_3F      => X"0000000000000000000000000000000000000000000000000000000000000000"
355 
      )
356 
    port map(
357 
      -- read
358 
      DIA   => (others => '0'),         -- 2-bit Data Input
359 
      DIPA  => (others => '0'),
360 
      ENA   => '1',                     -- RAM Enable Input
361 
      WEA   => '0',                     -- Write Enable Input
362 
      SSRA  => i_SSR,                   -- Synchronous Set/Reset Input
363 
      CLKA  => i_clock_r,               -- Clock
364 
      ADDRA => i_ADDR_r(12 downto 2),   -- 11-bit Address Input
365 
      DOA   => s2_DO_r,                 -- 8-bit Data Output
366 
      DOPA  => open,
367 
 
368 
      -- read/write
369 
      DIB   => i_DI_rw(23 downto 16),   -- 8-bit Data Input
370 
      DIPB  => (others => '0'),
371 
      ENB   => i_EN_rw,                 -- RAM Enable Input
372 
      WEB   => i_WE_rw(2),              -- Write Enable Input
373 
      SSRB  => i_SSR,                   -- Synchronous Set/Reset Input
374 
      CLKB  => i_clock_rw,              -- Clock
375 
      ADDRB => i_ADDR_rw,               -- 11-bit Address Input
376 
      DOB   => o_DI_rw(23 downto 16),   -- 8-bit Data Input
377 
      DOPB  => open
378 
      );
379 
 
380 
  u3_chars_ram : RAMB16_S9_S9
381 
    generic map (
382 
      WRITE_MODE_A => "WRITE_FIRST",   --  WRITE_FIRST, READ_FIRST or NO_CHANGE
383 
      INIT_A       => B"000000000",  --  Value of output RAM registers at startup
384 
      SRVAL_A      => B"000000000",     --  Ouput value upon SSR assertion
385 
      WRITE_MODE_B => "WRITE_FIRST",   --  WRITE_FIRST, READ_FIRST or NO_CHANGE
386 
      INIT_B       => B"000000000",  --  Value of output RAM registers at startup
387 
      SRVAL_B      => B"000000000",     --  Ouput value upon SSR assertion
388 
      --
389 
      INIT_00      => X"0000000000000000000000000000000000000000000000000000000000000000",
390 
      INIT_01      => X"0000000000000000000000000000000000000000000000000000000000000000",
391 
      INIT_02      => X"0000000000000000000000000000000000000000000000000000000000000000",
392 
      INIT_03      => X"0000000000000000000000000000000000000000000000000000000000000000",
393 
      INIT_04      => X"0000000000000000000000000000000000000000000000000000000000000000",
394 
      INIT_05      => X"0000000000000000000000000000000000000000000000000000000000000000",
395 
      INIT_06      => X"0000000000000000000000000000000000000000000000000000000000000000",
396 
      INIT_07      => X"0000000000000000000000000000000000000000000000000000000000000000",
397 
      INIT_08      => X"0000000000000000000000000000000000000000000000000000000000000000",
398 
      INIT_09      => X"0000000000000000000000000000000000000000000000000000000000000000",
399 
      INIT_0A      => X"0000000000000000000000000000000000000000000000000000000000000000",
400 
      INIT_0B      => X"0000000000000000000000000000000000000000000000000000000000000000",
401 
      INIT_0C      => X"0000000000000000000000000000000000000000000000000000000000000000",
402 
      INIT_0D      => X"0000000000000000000000000000000000000000000000000000000000000000",
403 
      INIT_0E      => X"0000000000000000000000000000000000000000000000000000000000000000",
404 
      INIT_0F      => X"0000000000000000000000000000000000000000000000000000000000000000",
405 
      INIT_10      => X"0000000000000000000000000000000000000000000000000000000000000000",
406 
      INIT_11      => X"0000000000000000000000000000000000000000000000000000000000000000",
407 
      INIT_12      => X"0000000000000000000000000000000000000000000000000000000000000000",
408 
      INIT_13      => X"0000000000000000000000000000000000000000000000000000000000000000",
409 
      INIT_14      => X"0000000000000000000000000000000000000000000000000000000000000000",
410 
      INIT_15      => X"0000000000000000000000000000000000000000000000000000000000000000",
411 
      INIT_16      => X"0000000000000000000000000000000000000000000000000000000000000000",
412 
      INIT_17      => X"0000000000000000000000000000000000000000000000000000000000000000",
413 
      INIT_18      => X"0000000000000000000000000000000000000000000000000000000000000000",
414 
      INIT_19      => X"0000000000000000000000000000000000000000000000000000000000000000",
415 
      INIT_1A      => X"0000000000000000000000000000000000000000000000000000000000000000",
416 
      INIT_1B      => X"0000000000000000000000000000000000000000000000000000000000000000",
417 
      INIT_1C      => X"0000000000000000000000000000000000000000000000000000000000000000",
418 
      INIT_1D      => X"0000000000000000000000000000000000000000000000000000000000000000",
419 
      INIT_1E      => X"0000000000000000000000000000000000000000000000000000000000000000",
420 
      INIT_1F      => X"0000000000000000000000000000000000000000000000000000000000000000",
421 
      INIT_20      => X"0000000000000000000000000000000000000000000000000000000000000000",
422 
      INIT_21      => X"0000000000000000000000000000000000000000000000000000000000000000",
423 
      INIT_22      => X"0000000000000000000000000000000000000000000000000000000000000000",
424 
      INIT_23      => X"0000000000000000000000000000000000000000000000000000000000000000",
425 
      INIT_24      => X"0000000000000000000000000000000000000000000000000000000000000000",
426 
      INIT_25      => X"0000000000000000000000000000000000000000000000000000000000000000",
427 
      INIT_26      => X"0000000000000000000000000000000000000000000000000000000000000000",
428 
      INIT_27      => X"0000000000000000000000000000000000000000000000000000000000000000",
429 
      INIT_28      => X"0000000000000000000000000000000000000000000000000000000000000000",
430 
      INIT_29      => X"0000000000000000000000000000000000000000000000000000000000000000",
431 
      INIT_2A      => X"0000000000000000000000000000000000000000000000000000000000000000",
432 
      INIT_2B      => X"0000000000000000000000000000000000000000000000000000000000000000",
433 
      INIT_2C      => X"0000000000000000000000000000000000000000000000000000000000000000",
434 
      INIT_2D      => X"0000000000000000000000000000000000000000000000000000000000000000",
435 
      INIT_2E      => X"0000000000000000000000000000000000000000000000000000000000000000",
436 
      INIT_2F      => X"0000000000000000000000000000000000000000000000000000000000000000",
437 
      INIT_30      => X"0000000000000000000000000000000000000000000000000000000000000000",
438 
      INIT_31      => X"0000000000000000000000000000000000000000000000000000000000000000",
439 
      INIT_32      => X"0000000000000000000000000000000000000000000000000000000000000000",
440 
      INIT_33      => X"0000000000000000000000000000000000000000000000000000000000000000",
441 
      INIT_34      => X"0000000000000000000000000000000000000000000000000000000000000000",
442 
      INIT_35      => X"0000000000000000000000000000000000000000000000000000000000000000",
443 
      INIT_36      => X"0000000000000000000000000000000000000000000000000000000000000000",
444 
      INIT_37      => X"0000000000000000000000000000000000000000000000000000000000000000",
445 
      INIT_38      => X"0000000000000000000000000000000000000000000000000000000000000000",
446 
      INIT_39      => X"0000000000000000000000000000000000000000000000000000000000000000",
447 
      INIT_3A      => X"0000000000000000000000000000000000000000000000000000000000000000",
448 
      INIT_3B      => X"0000000000000000000000000000000000000000000000000000000000000000",
449 
      INIT_3C      => X"0000000000000000000000000000000000000000000000000000000000000000",
450 
      INIT_3D      => X"0000000000000000000000000000000000000000000000000000000000000000",
451 
      INIT_3E      => X"0000000000000000000000000000000000000000000000000000000000000000",
452 
      INIT_3F      => X"0000000000000000000000000000000000000000000000000000000000000000"
453 
      )
454 
    port map(
455 
      -- read
456 
      DIA   => (others => '0'),         -- 2-bit Data Input
457 
      DIPA  => (others => '0'),
458 
      ENA   => '1',                     -- RAM Enable Input
459 
      WEA   => '0',                     -- Write Enable Input
460 
      SSRA  => i_SSR,                   -- Synchronous Set/Reset Input
461 
      CLKA  => i_clock_r,               -- Clock
462 
      ADDRA => i_ADDR_r(12 downto 2),   -- 11-bit Address Input
463 
      DOA   => s3_DO_r,                 -- 8-bit Data Output
464 
      DOPA  => open,
465 
 
466 
      -- read/write
467 
      DIB   => i_DI_rw(31 downto 24),   -- 8-bit Data Input
468 
      DIPB  => (others => '0'),
469 
      ENB   => i_EN_rw,                 -- RAM Enable Input
470 
      WEB   => i_WE_rw(3),              -- Write Enable Input
471 
      SSRB  => i_SSR,                   -- Synchronous Set/Reset Input
472 
      CLKB  => i_clock_rw,              -- Clock
473 
      ADDRB => i_ADDR_rw,               -- 11-bit Address Input
474 
      DOB   => o_DI_rw(31 downto 24),   -- 8-bit Data Input
475 
      DOPB  => open
476 
      );
477 
 
478 
  o_DO_r <= s0_DO_r when i_ADDR_r(1 downto 0) = "11" else
479 
            s1_DO_r when i_ADDR_r(1 downto 0) = "10" else
480 
            s2_DO_r when i_ADDR_r(1 downto 0) = "01" else
481 
            s3_DO_r when i_ADDR_r(1 downto 0) = "00" else
482 
            (others => 'X');
483 
 
484 
end rtl;

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