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--------------------------------------------------------------------------------
----                                                                        ----
---- This file is part of the yaVGA project                                 ----
---- http://www.opencores.org/?do=project&who=yavga                         ----
----                                                                        ----
---- Description                                                            ----
---- Implementation of yaVGA IP core                                        ----
----                                                                        ----
---- To Do:                                                                 ----
----                                                                        ----
----                                                                        ----
---- Author(s):                                                             ----
---- Sandro Amato, sdroamt@netscape.net                                     ----
----                                                                        ----
--------------------------------------------------------------------------------
----                                                                        ----
---- Copyright (c) 2009, Sandro Amato                                       ----
---- All rights reserved.                                                   ----
----                                                                        ----
---- Redistribution  and  use in  source  and binary forms, with or without ----
---- modification,  are  permitted  provided that  the following conditions ----
---- are met:                                                               ----
----                                                                        ----
----     * Redistributions  of  source  code  must  retain the above        ----
----       copyright   notice,  this  list  of  conditions  and  the        ----
----       following disclaimer.                                            ----
----     * Redistributions  in  binary form must reproduce the above        ----
----       copyright   notice,  this  list  of  conditions  and  the        ----
----       following  disclaimer in  the documentation and/or  other        ----
----       materials provided with the distribution.                        ----
----     * Neither  the  name  of  SANDRO AMATO nor the names of its        ----
----       contributors may be used to  endorse or  promote products        ----
----       derived from this software without specific prior written        ----
----       permission.                                                      ----
----                                                                        ----
---- THIS SOFTWARE IS PROVIDED  BY THE COPYRIGHT  HOLDERS AND  CONTRIBUTORS ----
---- "AS IS"  AND  ANY EXPRESS OR  IMPLIED  WARRANTIES, INCLUDING,  BUT NOT ----
---- LIMITED  TO, THE  IMPLIED  WARRANTIES  OF MERCHANTABILITY  AND FITNESS ----
---- FOR  A PARTICULAR  PURPOSE  ARE  DISCLAIMED. IN  NO  EVENT  SHALL  THE ----
---- COPYRIGHT  OWNER  OR CONTRIBUTORS  BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL,  SPECIAL,  EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, ----
---- BUT  NOT LIMITED  TO,  PROCUREMENT OF  SUBSTITUTE  GOODS  OR SERVICES; ----
---- LOSS  OF  USE,  DATA,  OR PROFITS;  OR  BUSINESS INTERRUPTION) HOWEVER ----
---- CAUSED  AND  ON  ANY THEORY  OF LIABILITY, WHETHER IN CONTRACT, STRICT ----
---- LIABILITY,  OR  TORT  (INCLUDING  NEGLIGENCE  OR OTHERWISE) ARISING IN ----
---- ANY  WAY OUT  OF THE  USE  OF  THIS  SOFTWARE,  EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE.                                            ----
--------------------------------------------------------------------------------
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
 
use work.yavga_pkg.all;
 
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity chars_RAM is
  port (
    i_clock_rw : in  std_logic;         -- Write Clock
    i_EN_rw    : in  std_logic;         -- Write RAM Enable Input
    i_WE_rw    : in  std_logic_vector(c_CHR_WE_BUS_W - 1 downto 0);  -- Write Enable Input
    i_ADDR_rw  : in  std_logic_vector(10 downto 0);  -- Write 11-bit Address Input
    i_DI_rw    : in  std_logic_vector(31 downto 0);  -- Write 32-bit Data Input
    o_DI_rw    : out std_logic_vector(31 downto 0);  -- Write 32-bit Data Input
 
    i_SSR : in std_logic;               -- Synchronous Set/Reset Input
 
    i_clock_r : in  std_logic;          -- Read Clock
    i_EN_r    : in  std_logic;
    i_ADDR_r  : in  std_logic_vector(12 downto 0);  -- Read 13-bit Address Input
    o_DO_r    : out std_logic_vector(7 downto 0)    -- Read 8-bit Data Output
    );
end chars_RAM;
 
architecture Behavioral of chars_RAM is
  signal s0_DO_r : std_logic_vector(7 downto 0);
  signal s1_DO_r : std_logic_vector(7 downto 0);
  signal s2_DO_r : std_logic_vector(7 downto 0);
  signal s3_DO_r : std_logic_vector(7 downto 0);
 
  constant c_ram_size : natural := 2**(c_CHR_ADDR_BUS_W);
 
  type t_ram is array (c_ram_size-1 downto 0) of
    std_logic_vector (c_INTCHR_DATA_BUS_W - 1 downto 0);
 
  shared variable v_ram0 : t_ram := (
    27     => X"05",  -- config "bg and curs color" (108/4 = 27)
    1126   => X"53",                    -- S
    1127   => X"72",                    -- r
    1128   => X"6D",                    -- m
    1129   => X"20",                    --  
    1130   => X"64",                    -- d
    1131   => X"6D",                    -- m
    1132   => X"65",                    -- e
    1133   => X"61",                    -- a
    1134   => X"6E",                    -- n
    others => X"00"
    );
 
  shared variable v_ram1 : t_ram := (
    27     => X"07",  -- config "xy coords spans on three bytes" (108/4 = 27)
    1126   => X"61",                    -- a
    1127   => X"6F",                    -- o
    1128   => X"61",                    -- a
    1129   => X"2D",                    -- -
    1130   => X"72",                    -- r
    1131   => X"74",                    -- t
    1132   => X"74",                    -- t
    1133   => X"70",                    -- p
    1134   => X"65",                    -- e
    others => X"00"
    );
 
  shared variable v_ram2 : t_ram := (
    27     => X"09",  -- config "xy coords spans on three bytes" (108/4 = 27)
    1126   => X"6E",                    -- n
    1127   => X"20",                    --  
    1128   => X"74",                    -- t
    1129   => X"20",                    --  
    1130   => X"6F",                    -- o
    1131   => X"40",                    -- @
    1132   => X"73",                    -- s
    1133   => X"65",                    -- e
    1134   => X"74",                    -- t
    others => X"00"
    );
 
  shared variable v_ram3 : t_ram := (
    27     => X"5E",  -- config "xy coords spans on three bytes" (108/4 = 27)
    1126   => X"64",                    -- d
    1127   => X"41",                    -- A
    1128   => X"6F",                    -- o
    1129   => X"73",                    -- s
    1130   => X"61",                    -- a
    1131   => X"6E",                    -- n
    1132   => X"63",                    -- c
    1133   => X"2E",                    -- .
    1134   => X"20",                    --  
    others => X"00"
    );
 
begin
 
  p_rw0_port : process (i_clock_rw)
  begin
    if rising_edge(i_clock_rw) then
      if i_SSR = '1' then
        o_DI_rw(31 downto 24) <= (others => '0');
      elsif (i_EN_rw = '1') then
        o_DI_rw(31 downto 24) <= v_ram0(conv_integer(i_ADDR_rw));
        if (i_WE_rw(0) = '1') then
          v_ram0(conv_integer(i_ADDR_rw)) := i_DI_rw(31 downto 24);
        end if;
      end if;
    end if;
  end process;
 
  p_rw1_port : process (i_clock_rw)
  begin
    if rising_edge(i_clock_rw) then
      if i_SSR = '1' then
        o_DI_rw(23 downto 16) <= (others => '0');
      elsif (i_EN_rw = '1') then
        o_DI_rw(23 downto 16) <= v_ram1(conv_integer(i_ADDR_rw));
        if (i_WE_rw(1) = '1') then
          v_ram1(conv_integer(i_ADDR_rw)) := i_DI_rw(23 downto 16);
        end if;
      end if;
    end if;
  end process;
 
  p_rw2_port : process (i_clock_rw)
  begin
    if rising_edge(i_clock_rw) then
      if i_SSR = '1' then
        o_DI_rw(15 downto 8) <= (others => '0');
      elsif (i_EN_rw = '1') then
        o_DI_rw(15 downto 8) <= v_ram2(conv_integer(i_ADDR_rw));
        if (i_WE_rw(2) = '1') then
          v_ram2(conv_integer(i_ADDR_rw)) := i_DI_rw(15 downto 8);
        end if;
      end if;
    end if;
  end process;
 
  p_rw3_port : process (i_clock_rw)
  begin
    if rising_edge(i_clock_rw) then
      if i_SSR = '1' then
        o_DI_rw(7 downto 0) <= (others => '0');
      elsif (i_EN_rw = '1') then
        o_DI_rw(7 downto 0) <= v_ram3(conv_integer(i_ADDR_rw));
        if (i_WE_rw(3) = '1') then
          v_ram3(conv_integer(i_ADDR_rw)) := i_DI_rw(7 downto 0);
        end if;
      end if;
    end if;
  end process;
 
 
  p_ro0_port : process (i_clock_r)
  begin
    if rising_edge(i_clock_r) then
      if i_SSR = '1' then
        s0_DO_r <= (others => '0');
      elsif (i_EN_r = '1') then
        s0_DO_r <= v_ram0(conv_integer(i_ADDR_r(i_ADDR_r'left downto 2)));
      end if;
    end if;
  end process;
 
  p_ro1_port : process (i_clock_r)
  begin
    if rising_edge(i_clock_r) then
      if i_SSR = '1' then
        s1_DO_r <= (others => '0');
      elsif (i_EN_r = '1') then
        s1_DO_r <= v_ram1(conv_integer(i_ADDR_r(i_ADDR_r'left downto 2)));
      end if;
    end if;
  end process;
 
  p_ro2_port : process (i_clock_r)
  begin
    if rising_edge(i_clock_r) then
      if i_SSR = '1' then
        s2_DO_r <= (others => '0');
      elsif (i_EN_r = '1') then
        s2_DO_r <= v_ram2(conv_integer(i_ADDR_r(i_ADDR_r'left downto 2)));
      end if;
    end if;
  end process;
 
  p_ro3_port : process (i_clock_r)
  begin
    if rising_edge(i_clock_r) then
      if i_SSR = '1' then
        s3_DO_r <= (others => '0');
      elsif (i_EN_r = '1') then
        s3_DO_r <= v_ram3(conv_integer(i_ADDR_r(i_ADDR_r'left downto 2)));
      end if;
    end if;
  end process;
 
  o_DO_r <=
    s0_DO_r when i_ADDR_r(1 downto 0) = "00" else
    s1_DO_r when i_ADDR_r(1 downto 0) = "01" else
    s2_DO_r when i_ADDR_r(1 downto 0) = "10" else
    s3_DO_r when i_ADDR_r(1 downto 0) = "11" else
    (others => 'X');
end Behavioral;

Line No.	Rev	Author	Line
1	2	sandroamt	`--------------------------------------------------------------------------------`
2			`---- ----`
3			`---- This file is part of the yaVGA project ----`
4			`---- http://www.opencores.org/?do=project&who=yavga ----`
5			`---- ----`
6			`---- Description ----`
7			`---- Implementation of yaVGA IP core ----`
8			`---- ----`
9			`---- To Do: ----`
10			`---- ----`
11			`---- ----`
12			`---- Author(s): ----`
13			`---- Sandro Amato, sdroamt@netscape.net ----`
14			`---- ----`
15			`--------------------------------------------------------------------------------`
16			`---- ----`
17			`---- Copyright (c) 2009, Sandro Amato ----`
18			`---- All rights reserved. ----`
19			`---- ----`
20			`---- Redistribution and use in source and binary forms, with or without ----`
21			`---- modification, are permitted provided that the following conditions ----`
22			`---- are met: ----`
23			`---- ----`
24			`---- * Redistributions of source code must retain the above ----`
25			`---- copyright notice, this list of conditions and the ----`
26			`---- following disclaimer. ----`
27			`---- * Redistributions in binary form must reproduce the above ----`
28			`---- copyright notice, this list of conditions and the ----`
29			`---- following disclaimer in the documentation and/or other ----`
30			`---- materials provided with the distribution. ----`
31			`---- * Neither the name of SANDRO AMATO nor the names of its ----`
32			`---- contributors may be used to endorse or promote products ----`
33			`---- derived from this software without specific prior written ----`
34			`---- permission. ----`
35			`---- ----`
36			`---- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ----`
37			`---- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ----`
38			`---- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----`
39			`---- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ----`
40			`---- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----`
41			`---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, ----`
42			`---- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ----`
43			`---- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ----`
44			`---- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ----`
45			`---- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ----`
46			`---- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----`
47			`---- POSSIBILITY OF SUCH DAMAGE. ----`
48			`--------------------------------------------------------------------------------`
49
50
51			`library IEEE;`
52			`use IEEE.STD_LOGIC_1164.all;`
53			`use IEEE.STD_LOGIC_ARITH.all;`
54			`use IEEE.STD_LOGIC_UNSIGNED.all;`
55
56	28	sandroamt	`use work.yavga_pkg.all;`
57
58	2	sandroamt	`-- Uncomment the following lines to use the declarations that are`
59			`-- provided for instantiating Xilinx primitive components.`
60	36	sandroamt	`--library UNISIM;`
61			`--use UNISIM.VComponents.all;`
62	2	sandroamt
63			`entity chars_RAM is`
64			`port (`
65			`i_clock_rw : in std_logic; -- Write Clock`
66			`i_EN_rw : in std_logic; -- Write RAM Enable Input`
67	28	sandroamt	`i_WE_rw : in std_logic_vector(c_CHR_WE_BUS_W - 1 downto 0); -- Write Enable Input`
68	2	sandroamt	`i_ADDR_rw : in std_logic_vector(10 downto 0); -- Write 11-bit Address Input`
69			`i_DI_rw : in std_logic_vector(31 downto 0); -- Write 32-bit Data Input`
70			`o_DI_rw : out std_logic_vector(31 downto 0); -- Write 32-bit Data Input`
71
72			`i_SSR : in std_logic; -- Synchronous Set/Reset Input`
73
74			`i_clock_r : in std_logic; -- Read Clock`
75	23	sandroamt	`i_EN_r : in std_logic;`
76	2	sandroamt	`i_ADDR_r : in std_logic_vector(12 downto 0); -- Read 13-bit Address Input`
77			`o_DO_r : out std_logic_vector(7 downto 0) -- Read 8-bit Data Output`
78			`);`
79			`end chars_RAM;`
80
81	36	sandroamt	`architecture Behavioral of chars_RAM is`
82	2	sandroamt	`signal s0_DO_r : std_logic_vector(7 downto 0);`
83			`signal s1_DO_r : std_logic_vector(7 downto 0);`
84			`signal s2_DO_r : std_logic_vector(7 downto 0);`
85			`signal s3_DO_r : std_logic_vector(7 downto 0);`
86
87	36	sandroamt	`constant c_ram_size : natural := 2**(c_CHR_ADDR_BUS_W);`
88
89			`type t_ram is array (c_ram_size-1 downto 0) of`
90			`std_logic_vector (c_INTCHR_DATA_BUS_W - 1 downto 0);`
91
92			`shared variable v_ram0 : t_ram := (`
93			`27 => X"05", -- config "bg and curs color" (108/4 = 27)`
94			`1126 => X"53", -- S`
95			`1127 => X"72", -- r`
96			`1128 => X"6D", -- m`
97			`1129 => X"20", --`
98			`1130 => X"64", -- d`
99			`1131 => X"6D", -- m`
100			`1132 => X"65", -- e`
101			`1133 => X"61", -- a`
102			`1134 => X"6E", -- n`
103			`others => X"00"`
104			`);`
105
106			`shared variable v_ram1 : t_ram := (`
107			`27 => X"07", -- config "xy coords spans on three bytes" (108/4 = 27)`
108			`1126 => X"61", -- a`
109			`1127 => X"6F", -- o`
110			`1128 => X"61", -- a`
111			`1129 => X"2D", -- -`
112			`1130 => X"72", -- r`
113			`1131 => X"74", -- t`
114			`1132 => X"74", -- t`
115			`1133 => X"70", -- p`
116			`1134 => X"65", -- e`
117			`others => X"00"`
118			`);`
119
120			`shared variable v_ram2 : t_ram := (`
121			`27 => X"09", -- config "xy coords spans on three bytes" (108/4 = 27)`
122			`1126 => X"6E", -- n`
123			`1127 => X"20", --`
124			`1128 => X"74", -- t`
125			`1129 => X"20", --`
126			`1130 => X"6F", -- o`
127			`1131 => X"40", -- @`
128			`1132 => X"73", -- s`
129			`1133 => X"65", -- e`
130			`1134 => X"74", -- t`
131			`others => X"00"`
132			`);`
133
134			`shared variable v_ram3 : t_ram := (`
135			`27 => X"5E", -- config "xy coords spans on three bytes" (108/4 = 27)`
136			`1126 => X"64", -- d`
137			`1127 => X"41", -- A`
138			`1128 => X"6F", -- o`
139			`1129 => X"73", -- s`
140			`1130 => X"61", -- a`
141			`1131 => X"6E", -- n`
142			`1132 => X"63", -- c`
143			`1133 => X"2E", -- .`
144			`1134 => X"20", --`
145			`others => X"00"`
146			`);`
147
148	2	sandroamt	`begin`
149
150	36	sandroamt	`p_rw0_port : process (i_clock_rw)`
151			`begin`
152			`if rising_edge(i_clock_rw) then`
153			`if i_SSR = '1' then`
154			`o_DI_rw(31 downto 24) <= (others => '0');`
155			`elsif (i_EN_rw = '1') then`
156			`o_DI_rw(31 downto 24) <= v_ram0(conv_integer(i_ADDR_rw));`
157			`if (i_WE_rw(0) = '1') then`
158			`v_ram0(conv_integer(i_ADDR_rw)) := i_DI_rw(31 downto 24);`
159			`end if;`
160			`end if;`
161			`end if;`
162			`end process;`
163	2	sandroamt
164	36	sandroamt	`p_rw1_port : process (i_clock_rw)`
165			`begin`
166			`if rising_edge(i_clock_rw) then`
167			`if i_SSR = '1' then`
168			`o_DI_rw(23 downto 16) <= (others => '0');`
169			`elsif (i_EN_rw = '1') then`
170			`o_DI_rw(23 downto 16) <= v_ram1(conv_integer(i_ADDR_rw));`
171			`if (i_WE_rw(1) = '1') then`
172			`v_ram1(conv_integer(i_ADDR_rw)) := i_DI_rw(23 downto 16);`
173			`end if;`
174			`end if;`
175			`end if;`
176			`end process;`
177	2	sandroamt
178	36	sandroamt	`p_rw2_port : process (i_clock_rw)`
179			`begin`
180			`if rising_edge(i_clock_rw) then`
181			`if i_SSR = '1' then`
182			`o_DI_rw(15 downto 8) <= (others => '0');`
183			`elsif (i_EN_rw = '1') then`
184			`o_DI_rw(15 downto 8) <= v_ram2(conv_integer(i_ADDR_rw));`
185			`if (i_WE_rw(2) = '1') then`
186			`v_ram2(conv_integer(i_ADDR_rw)) := i_DI_rw(15 downto 8);`
187			`end if;`
188			`end if;`
189			`end if;`
190			`end process;`
191	2	sandroamt
192	36	sandroamt	`p_rw3_port : process (i_clock_rw)`
193			`begin`
194			`if rising_edge(i_clock_rw) then`
195			`if i_SSR = '1' then`
196			`o_DI_rw(7 downto 0) <= (others => '0');`
197			`elsif (i_EN_rw = '1') then`
198			`o_DI_rw(7 downto 0) <= v_ram3(conv_integer(i_ADDR_rw));`
199			`if (i_WE_rw(3) = '1') then`
200			`v_ram3(conv_integer(i_ADDR_rw)) := i_DI_rw(7 downto 0);`
201			`end if;`
202			`end if;`
203			`end if;`
204			`end process;`
205	2	sandroamt
206
207	36	sandroamt	`p_ro0_port : process (i_clock_r)`
208			`begin`
209			`if rising_edge(i_clock_r) then`
210			`if i_SSR = '1' then`
211			`s0_DO_r <= (others => '0');`
212			`elsif (i_EN_r = '1') then`
213			`s0_DO_r <= v_ram0(conv_integer(i_ADDR_r(i_ADDR_r'left downto 2)));`
214			`end if;`
215			`end if;`
216			`end process;`
217	2	sandroamt
218	36	sandroamt	`p_ro1_port : process (i_clock_r)`
219			`begin`
220			`if rising_edge(i_clock_r) then`
221			`if i_SSR = '1' then`
222			`s1_DO_r <= (others => '0');`
223			`elsif (i_EN_r = '1') then`
224			`s1_DO_r <= v_ram1(conv_integer(i_ADDR_r(i_ADDR_r'left downto 2)));`
225			`end if;`
226			`end if;`
227			`end process;`
228	2	sandroamt
229	36	sandroamt	`p_ro2_port : process (i_clock_r)`
230			`begin`
231			`if rising_edge(i_clock_r) then`
232			`if i_SSR = '1' then`
233			`s2_DO_r <= (others => '0');`
234			`elsif (i_EN_r = '1') then`
235			`s2_DO_r <= v_ram2(conv_integer(i_ADDR_r(i_ADDR_r'left downto 2)));`
236			`end if;`
237			`end if;`
238			`end process;`
239	2	sandroamt
240	36	sandroamt	`p_ro3_port : process (i_clock_r)`
241			`begin`
242			`if rising_edge(i_clock_r) then`
243			`if i_SSR = '1' then`
244			`s3_DO_r <= (others => '0');`
245			`elsif (i_EN_r = '1') then`
246			`s3_DO_r <= v_ram3(conv_integer(i_ADDR_r(i_ADDR_r'left downto 2)));`
247			`end if;`
248			`end if;`
249			`end process;`
250	2	sandroamt
251	36	sandroamt	`o_DO_r <=`
252			`s0_DO_r when i_ADDR_r(1 downto 0) = "00" else`
253			`s1_DO_r when i_ADDR_r(1 downto 0) = "01" else`
254			`s2_DO_r when i_ADDR_r(1 downto 0) = "10" else`
255			`s3_DO_r when i_ADDR_r(1 downto 0) = "11" else`
256			`(others => 'X');`
257			`end Behavioral;`

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[/] [yavga/] [trunk/] [vhdl/] [chars_RAM.vhd] - Blame information for rev 36