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[/] [yavga/] [trunk/] [vhdl/] [s3e_starter_1600k.ucf] - Blame information for rev 22

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1 2 sandroamt
################################################################################
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####                                                                        ####
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#### This file is part of the yaVGA project                                 ####
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#### http://www.opencores.org/?do=project&who=yavga                         ####
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####                                                                        ####
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#### Description                                                            ####
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#### Implementation of yaVGA IP core                                        ####
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####                                                                        ####
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#### To Do:                                                                 ####
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####                                                                        ####
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####                                                                        ####
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#### Author(s):                                                             ####
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#### Sandro Amato, sdroamt@netscape.net                                     ####
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####                                                                        ####
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################################################################################
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####                                                                        ####
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#### Copyright (c) 2009, Sandro Amato                                       ####
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#### All rights reserved.                                                   ####
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####                                                                        ####
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#### Redistribution  and  use in  source  and binary forms, with or without ####
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#### modification,  are  permitted  provided that  the following conditions ####
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#### are met:                                                               ####
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####                                                                        ####
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####     * Redistributions  of  source  code  must  retain the above        ####
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####       copyright   notice,  this  list  of  conditions  and  the        ####
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####       following disclaimer.                                            ####
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####     * Redistributions  in  binary form must reproduce the above        ####
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####       copyright   notice,  this  list  of  conditions  and  the        ####
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####       following  disclaimer in  the documentation and/or  other        ####
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####       materials provided with the distribution.                        ####
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####     * Neither  the  name  of  SANDRO AMATO nor the names of its        ####
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####       contributors may be used to  endorse or  promote products        ####
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####       derived from this software without specific prior written        ####
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####       permission.                                                      ####
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####                                                                        ####
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#### THIS SOFTWARE IS PROVIDED  BY THE COPYRIGHT  HOLDERS AND  CONTRIBUTORS ####
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#### "AS IS"  AND  ANY EXPRESS OR  IMPLIED  WARRANTIES, INCLUDING,  BUT NOT ####
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#### LIMITED  TO, THE  IMPLIED  WARRANTIES  OF MERCHANTABILITY  AND FITNESS ####
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#### FOR  A PARTICULAR  PURPOSE  ARE  DISCLAIMED. IN  NO  EVENT  SHALL  THE ####
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#### COPYRIGHT  OWNER  OR CONTRIBUTORS  BE LIABLE FOR ANY DIRECT, INDIRECT, ####
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#### INCIDENTAL,  SPECIAL,  EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, ####
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#### BUT  NOT LIMITED  TO,  PROCUREMENT OF  SUBSTITUTE  GOODS  OR SERVICES; ####
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#### LOSS  OF  USE,  DATA,  OR PROFITS;  OR  BUSINESS INTERRUPTION) HOWEVER ####
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#### CAUSED  AND  ON  ANY THEORY  OF LIABILITY, WHETHER IN CONTRACT, STRICT ####
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#### LIABILITY,  OR  TORT  (INCLUDING  NEGLIGENCE  OR OTHERWISE) ARISING IN ####
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#### ANY  WAY OUT  OF THE  USE  OF  THIS  SOFTWARE,  EVEN IF ADVISED OF THE ####
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#### POSSIBILITY OF SUCH DAMAGE.                                            ####
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################################################################################
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#PACE: Start of Constraints generated by PACE
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#PACE: Start of PACE I/O Pin Assignments
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NET "i_clk"  LOC = "c9" | IOSTANDARD = LVCMOS33 ;
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NET "o_b"  LOC = "g15" | IOSTANDARD = LVTTL  | DRIVE = 8  | SLEW = FAST ;
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NET "o_g"  LOC = "h15" | IOSTANDARD = LVTTL  | DRIVE = 8  | SLEW = FAST ;
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NET "o_hsync"  LOC = "f15" | IOSTANDARD = LVTTL  | DRIVE = 8  | SLEW = FAST ;
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NET "o_r"  LOC = "h14" | IOSTANDARD = LVTTL  | DRIVE = 8  | SLEW = FAST ;
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NET "o_vsync"  LOC = "f14" | IOSTANDARD = LVTTL  | DRIVE = 8  | SLEW = FAST ;
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#PACE: Start of PACE Area Constraints
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#AREA_GROUP "AG_u1_vga_ctrl" RANGE = SLICE_X84Y109:SLICE_X89Y100 ;
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#INST "u1_vga_ctrl" AREA_GROUP = "AG_u1_vga_ctrl" ;
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#PACE: Start of PACE Prohibit Constraints
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#PACE: End of Constraints generated by PACE

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