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[/] [yavga/] [trunk/] [vhdl/] [waveform_RAM.vhd] - Blame information for rev 28

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1 2 sandroamt 
--------------------------------------------------------------------------------
2 
----                                                                        ----
3 
---- This file is part of the yaVGA project                                 ----
4 
---- http://www.opencores.org/?do=project&who=yavga                         ----
5 
----                                                                        ----
6 
---- Description                                                            ----
7 
---- Implementation of yaVGA IP core                                        ----
8 
----                                                                        ----
9 
---- To Do:                                                                 ----
10 
----                                                                        ----
11 
----                                                                        ----
12 
---- Author(s):                                                             ----
13 
---- Sandro Amato, sdroamt@netscape.net                                     ----
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----                                                                        ----
15 
--------------------------------------------------------------------------------
16 
----                                                                        ----
17 
---- Copyright (c) 2009, Sandro Amato                                       ----
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---- All rights reserved.                                                   ----
19 
----                                                                        ----
20 
---- Redistribution  and  use in  source  and binary forms, with or without ----
21 
---- modification,  are  permitted  provided that  the following conditions ----
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---- are met:                                                               ----
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----                                                                        ----
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----     * Redistributions  of  source  code  must  retain the above        ----
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----       copyright   notice,  this  list  of  conditions  and  the        ----
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----       following disclaimer.                                            ----
27 
----     * Redistributions  in  binary form must reproduce the above        ----
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----       copyright   notice,  this  list  of  conditions  and  the        ----
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----       following  disclaimer in  the documentation and/or  other        ----
30 
----       materials provided with the distribution.                        ----
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----     * Neither  the  name  of  SANDRO AMATO nor the names of its        ----
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----       contributors may be used to  endorse or  promote products        ----
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----       derived from this software without specific prior written        ----
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----       permission.                                                      ----
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----                                                                        ----
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---- THIS SOFTWARE IS PROVIDED  BY THE COPYRIGHT  HOLDERS AND  CONTRIBUTORS ----
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---- "AS IS"  AND  ANY EXPRESS OR  IMPLIED  WARRANTIES, INCLUDING,  BUT NOT ----
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---- LIMITED  TO, THE  IMPLIED  WARRANTIES  OF MERCHANTABILITY  AND FITNESS ----
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---- FOR  A PARTICULAR  PURPOSE  ARE  DISCLAIMED. IN  NO  EVENT  SHALL  THE ----
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---- COPYRIGHT  OWNER  OR CONTRIBUTORS  BE LIABLE FOR ANY DIRECT, INDIRECT, ----
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---- INCIDENTAL,  SPECIAL,  EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, ----
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---- BUT  NOT LIMITED  TO,  PROCUREMENT OF  SUBSTITUTE  GOODS  OR SERVICES; ----
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---- LOSS  OF  USE,  DATA,  OR PROFITS;  OR  BUSINESS INTERRUPTION) HOWEVER ----
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---- CAUSED  AND  ON  ANY THEORY  OF LIABILITY, WHETHER IN CONTRACT, STRICT ----
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---- LIABILITY,  OR  TORT  (INCLUDING  NEGLIGENCE  OR OTHERWISE) ARISING IN ----
46 
---- ANY  WAY OUT  OF THE  USE  OF  THIS  SOFTWARE,  EVEN IF ADVISED OF THE ----
47 
---- POSSIBILITY OF SUCH DAMAGE.                                            ----
48 
--------------------------------------------------------------------------------
49 
 
50 
library IEEE;
51 
use IEEE.STD_LOGIC_1164.all;
52 
use IEEE.STD_LOGIC_ARITH.all;
53 
use IEEE.STD_LOGIC_UNSIGNED.all;
54 
 
55 28 sandroamt 
use work.yavga_pkg.all;
56 
 
57 2 sandroamt 
--  Uncomment the following lines to use the declarations that are
58 
--  provided for instantiating Xilinx primitive components.
59 
library UNISIM;
60 
use UNISIM.VComponents.all;
61 
 
62 
entity waveform_RAM is
63 
  port (
64 28 sandroamt 
    i_DIA    : in  std_logic_vector(c_WAVFRM_DATA_BUS_W - 1 downto 0);  -- 16-bit Data Input
65 2 sandroamt 
    -- i_DIPA   : in std_logic;                       -- 2-bit parity Input
66 
    -- i_ENA    : in std_logic;                       -- RAM Enable Input
67 28 sandroamt 
    i_WEA    : in  std_logic;           -- Write Enable Input
68 2 sandroamt 
    -- i_SSRA   : in std_logic;                       -- Synchronous Set/Reset Input
69 28 sandroamt 
    i_clockA : in  std_logic;           -- Clock
70 
    i_ADDRA  : in  std_logic_vector(c_WAVFRM_ADDR_BUS_W - 1 downto 0);  -- 10-bit Address Input
71 
    --o_DOA     : out std_logic_vector(c_WAVFRM_DATA_BUS_W - 1 downto 0);  -- 16-bit Data Output
72 2 sandroamt 
    -- o_DOPA   : out std_logic                       -- 2-bit parity Output
73 
    --
74 28 sandroamt 
    i_DIB    : in  std_logic_vector(c_WAVFRM_DATA_BUS_W - 1 downto 0);  -- 16-bit Data Input
75 2 sandroamt 
    -- i_DIPB   : in std_logic;                       -- 2-bit parity Input
76 
    -- i_ENB    : in std_logic;                       -- RAM Enable Input
77 28 sandroamt 
    i_WEB    : in  std_logic;           -- Write Enable Input
78 2 sandroamt 
    -- i_SSRB   : in std_logic;                       -- Synchronous Set/Reset Input
79 28 sandroamt 
    i_clockB : in  std_logic;           -- Clock
80 
    i_ADDRB  : in  std_logic_vector(c_WAVFRM_ADDR_BUS_W - 1 downto 0);  -- 10-bit Address Input
81 
    o_DOB    : out std_logic_vector(c_WAVFRM_DATA_BUS_W - 1 downto 0)  -- 16-bit Data Output
82 2 sandroamt 
    -- o_DOPB   : out std_logic                       -- 2-bit parity Output
83 
    );
84 
end waveform_RAM;
85 
 
86 
architecture rtl of waveform_RAM is
87 
 
88 
begin
89 
  -- wave form or video-line memory
90 
  -- |------| |-------------------------------------------|
91 
  -- | P  P | |  D  D  D |  D  D  D | D D D D D D D D D D |
92 
  -- |======| |===========================================|
93 
  -- |17 16 | | 15 14 13 | 12 11 10 | 9 8 7 6 5 4 3 2 1 0 |
94 
  -- |======| |===========================================|
95 
  -- | Free | |  Reserv. |  R  G  B |      vert. pos.     |
96 
  -- |------| |-------------------------------------------|
97 
  --
98 
 
99 
  Inst_waveform_RAM : RAMB16_S18_S18
100 
    generic map (
101 
      WRITE_MODE_A => "READ_FIRST",     -- "WRITE_FIRST";
102 
      INIT_A       => B"000000000000000000",
103 
      SRVAL_A      => B"000000000000000000",
104 
      --
105 
      WRITE_MODE_B => "READ_FIRST",     -- "WRITE_FIRST";
106 
      INIT_B       => B"000000000000000000",
107 
      SRVAL_B      => B"000000000000000000",
108 
      --
109 
      --INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
110 
      INIT_00      => X"112C112C112C112C112C112C112C112C112C112C112C112C112C112C112C112C",
111 
      INIT_01      => X"112D112D112D112D112D112D112D112D112D112D112D112D112D112D112D112D",
112 
      INIT_02      => X"112E112E112E112E112E112E112E112E112E112E112E112E112E112E112E112E",
113 
      INIT_03      => X"112F112F112F112F112F112F112F112F112F112F112F112F112F112F112F112F",
114 
      INIT_04      => X"112E112E112E112E112E112E112E112E112E112E112E112E112E112E112E112E",
115 
      INIT_05      => X"112D112D112D112D112D112D112D112D112D112D112D112D112D112D112D112D",
116 
      INIT_06      => X"112C112C112C112C112C112C112C112C112C112C112C112C112C112C112C112C",
117 
      INIT_07      => X"112B112B112B112B112B112B112B112B112B112B112B112B112B112B112B112B",
118 
 
119 
      --INIT_08 => X"112A112A112A112A112A112A112A112A112A112A112A112A112A112A112A112A",
120 
      INIT_08 => X"112A114011C211F4117C10FA110E112A112A112A112A112A112A112A112A192A",
121 
 
122 
      --INIT_09 => X"1129112911291129112911291129112911291129112911291129112911291129",
123 
      INIT_09 => X"1129112911291129112911291129112911291129112911291129112911291529",
124 
 
125 
      INIT_0A  => X"1128112811281128112811281128112811281128112811281128112811281128",
126 
      INIT_0B  => X"1127112711271127112711271127112711271127112711271127112711271127",
127 
      INIT_0C  => X"1126112611261126112611261126112611261126112611261126112611261126",
128 
      INIT_0D  => X"1125112511251125112511251125112511251125112511251125112511251125",
129 
      INIT_0E  => X"1124112411241124112411241124112411241124112411241124112411241124",
130 
      INIT_0F  => X"1123112311231123112311231123112311231123112311231123112311231123",
131 
      --
132 
      INIT_10  => X"1123112311231123112311231123112311231123112311231123112311231123",
133 
      INIT_11  => X"1124112411241124112411241124112411241124112411241124112411241124",
134 
      INIT_12  => X"1125112511251125112511251125112511251125112511251125112511251125",
135 
      INIT_13  => X"1126112611261126112611261126112611261126112611261126112611261126",
136 
      INIT_14  => X"1127112711271127112711271127112711271127112711271127112711271127",
137 
      INIT_15  => X"1128112811281128112811281128112811281128112811281128112811281128",
138 
      INIT_16  => X"1129112911291129112911291129112911291129112911291129112911291129",
139 
      INIT_17  => X"112A112A112A112A112A112A112A112A112A112A112A112A112A112A112A112A",
140 
      INIT_18  => X"112B112B112B112B112B112B112B112B112B112B112B112B112B112B112B112B",
141 
      INIT_19  => X"112C112C112C112C112C112C112C112C112C112C112C112C112C112C112C112C",
142 
      INIT_1A  => X"112D112D112D112D112D112D112D112D112D112D112D112D112D112D112D112D",
143 
      INIT_1B  => X"112E112E112E112E112E112E112E112E112E112E112E112E112E112E112E112E",
144 
      INIT_1C  => X"112F112F112F112F112F112F112F112F112F112F112F112F112F112F112F112F",
145 
      INIT_1D  => X"112E112E112E112E112E112E112E112E112E112E112E112E112E112E112E112E",
146 
      INIT_1E  => X"112D112D112D112D112D112D112D112D112D112D112D112D112D112D112D112D",
147 
      INIT_1F  => X"112C112C112C112C112C112C112C112C112C112C112C112C112C112C112C112C",
148 
      --
149 
      INIT_20  => X"112C112C112C112C112C112C112C112C112C112C112C112C112C112C112C112C",
150 
      INIT_21  => X"112D112D112D112D112D112D112D112D112D112D112D112D112D112D112D112D",
151 
      INIT_22  => X"112E112E112E112E112E112E112E112E112E112E112E112E112E112E112E112E",
152 
      INIT_23  => X"112F112F112F112F112F112F112F112F112F112F112F112F112F112F112F112F",
153 
      INIT_24  => X"112E112E112E112E112E112E112E112E112E112E112E112E112E112E112E112E",
154 
      INIT_25  => X"112D112D112D112D112D112D112D112D112D112D112D112D112D112D112D112D",
155 
      INIT_26  => X"112C112C112C112C112C112C112C112C112C112C112C112C112C112C112C112C",
156 
      INIT_27  => X"112B112B112B112B112B112B112B112B112B112B112B112B112B112B112B112B",
157 
      INIT_28  => X"112A112A112A112A112A112A112A112A112A112A112A112A112A112A112A112A",
158 
      INIT_29  => X"1129112911291129112911291129112911291129112911291129112911291129",
159 
      INIT_2A  => X"1128112811281128112811281128112811281128112811281128112811281128",
160 
      INIT_2B  => X"1127112711271127112711271127112711271127112711271127112711271127",
161 
      INIT_2C  => X"1126112611261126112611261126112611261126112611261126112611261126",
162 
      INIT_2D  => X"1125112511251125112511251125112511251125112511251125112511251125",
163 
      INIT_2E  => X"1124112411241124112411241124112411241124112411241124112411241124",
164 
      INIT_2F  => X"1123112311231123112311231123112311231123112311231123112311231123",
165 
      --
166 
      INIT_30  => X"1123112311231123112311231123112311231123112311231123112311231123",
167 
      INIT_31  => X"1124112411241124112411241124112411241124112411241124112411241124",
168 
      INIT_32  => X"1125112511251125112511251125112511251125112511251125112511251125",
169 
      INIT_33  => X"1126112611261126112611261126112611261126112611261126112611261126",
170 
      INIT_34  => X"1127112711271127112711271127112711271127112711271127112711271127",
171 
      INIT_35  => X"1128112811281128112811281128112811281128112811281128112811281128",
172 
      INIT_36  => X"1129112911291129112911291129112911291129112911291129112911291129",
173 
      INIT_37  => X"112A112A112A112A112A112A112A112A112A112A112A112A112A112A112A112A",
174 
      INIT_38  => X"112B112B112B112B112B112B112B112B112B112B112B112B112B112B112B112B",
175 
      INIT_39  => X"112C112C112C112C112C112C112C112C112C112C112C112C112C112C112C112C",
176 
      INIT_3A  => X"112D112D112D112D112D112D112D112D112D112D112D112D112D112D112D112D",
177 
      INIT_3B  => X"112E112E112E112E112E112E112E112E112E112E112E112E112E112E112E112E",
178 
      INIT_3C  => X"112F112F112F112F112F112F112F112F112F112F112F112F112F112F112F112F",
179 
      INIT_3D  => X"112E112E112E112E112E112E112E112E112E112E112E112E112E112E112E112E",
180 
      INIT_3E  => X"112D112D112D112D112D112D112D112D112D112D112D112D112D112D112D112D",
181 
      INIT_3F  => X"112C112C112C112C112C112C112C112C112C112C112C112C112C112C112C112C",
182 
      --
183 
      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
184 
      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
185 
      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
186 
      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
187 
      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
188 
      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
189 
      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
190 
      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000"
191 
      )
192 
    port map(
193 
      DIA   => i_DIA,                   -- 16 bit data Input
194 
      DIPA  => (others => '1'),         -- 2 bit data parity Input
195 
      ENA   => '1',                     -- 1-bit RAM enable Input
196 
      WEA   => i_WEA,                   -- 1-bit Write Enable Input
197 
      SSRA  => '0',                     -- 1-bit Synchronous Set/Reset Input
198 
      CLKA  => i_clockA,                -- 1-bit Clock Input
199 
      ADDRA => i_ADDRA,                 -- 10-bit Address Input
200 
      DOA   => open,  -- o_DOA,      -- 16-bit Data Output
201 
      DOPA  => open,                    -- 2-bit Data Parity Output
202 
      --
203 
      DIB   => i_DIB,                   -- 16 bit data Input
204 
      DIPB  => (others => '1'),         -- 2 bit data parity Input
205 
      ENB   => '1',                     -- 1-bit RAM enable Input
206 
      WEB   => i_WEB,                   -- 1-bit Write Enable Input
207 
      SSRB  => '0',                     -- 1-bit Synchronous Set/Reset Input
208 
      CLKB  => i_clockB,                -- 1-bit Clock Input
209 
      ADDRB => i_ADDRB,                 -- 10-bit Address Input
210 
      DOB   => o_DOB,                   -- 16-bit Data Output
211 
      DOPB  => open                     -- 2-bit Data Parity Output
212 
      );
213 
 
214 
end rtl;

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