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[/] [yifive/] [trunk/] [caravel_yifive/] [verilog/] [dv/] [la_test2/] [Makefile] - Blame information for rev 23

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# SPDX-FileCopyrightText: 2020 Efabless Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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#      http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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# SPDX-License-Identifier: Apache-2.0
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## Caravel Pointers
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CARAVEL_ROOT ?= ../../../caravel
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CARAVEL_PATH ?= $(CARAVEL_ROOT)
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CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel
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CARAVEL_VERILOG_PATH  = $(CARAVEL_PATH)/verilog
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CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl
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CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel
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## User Project Pointers
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UPRJ_VERILOG_PATH ?= ../../../verilog
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UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
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UPRJ_BEHAVIOURAL_MODELS = ../model
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UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/syntacore/scr1/src/includes
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UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
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## RISCV GCC
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GCC_PATH?=/ef/apps/bin
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GCC_PREFIX?=riscv32-unknown-elf
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PDK_PATH?=/ef/tech/SW/sky130A
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## Simulation mode: RTL/GL
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SIM?=RTL
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.SUFFIXES:
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PATTERN = la_test2
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all:  ${PATTERN:=.vcd}
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hex:  ${PATTERN:=.hex}
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vvp:  ${PATTERN:=.vvp}
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%.vvp: %_tb.v %.hex
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ifeq ($(SIM),RTL)
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        iverilog -g2005-sv -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
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        -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
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        -I $(UPRJ_BEHAVIOURAL_MODELS)    -I $(UPRJ_RTL_PATH) \
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        -I $(UPRJ_INCLUDE_PATH1)    -I $(UPRJ_INCLUDE_PATH2) \
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        $< -o $@
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else
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        iverilog -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
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        -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
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        -I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH)   -I $(UPRJ_VERILOG_PATH) \
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        $< -o $@
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endif
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%.vcd: %.vvp
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        vvp $<
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%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s
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        ${GCC_PATH}/${GCC_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $<
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%.hex: %.elf
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        ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
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        # to fix flash base address
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        sed -i 's/@10000000/@00000000/g' $@
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%.bin: %.elf
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        ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
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# ---- Clean ----
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clean:
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        rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
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.PHONY: clean hex all

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