| 1 |
22 |
dinesha |
/*
|
| 2 |
|
|
* SPDX-FileCopyrightText: 2020 Efabless Corporation
|
| 3 |
|
|
*
|
| 4 |
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
| 5 |
|
|
* you may not use this file except in compliance with the License.
|
| 6 |
|
|
* You may obtain a copy of the License at
|
| 7 |
|
|
*
|
| 8 |
|
|
* http://www.apache.org/licenses/LICENSE-2.0
|
| 9 |
|
|
*
|
| 10 |
|
|
* Unless required by applicable law or agreed to in writing, software
|
| 11 |
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
| 12 |
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
| 13 |
|
|
* See the License for the specific language governing permissions and
|
| 14 |
|
|
* limitations under the License.
|
| 15 |
|
|
* SPDX-License-Identifier: Apache-2.0
|
| 16 |
|
|
*/
|
| 17 |
|
|
|
| 18 |
|
|
// This include is relative to $CARAVEL_PATH (see Makefile)
|
| 19 |
|
|
#include "verilog/dv/caravel/defs.h"
|
| 20 |
|
|
#include "verilog/dv/caravel/stub.c"
|
| 21 |
|
|
|
| 22 |
|
|
// User Project Slaves (0x3000_0000)
|
| 23 |
|
|
#define reg_mprj_slave (*(volatile uint32_t*)0x30000000)
|
| 24 |
|
|
|
| 25 |
|
|
#define reg_mprj_globl_reg0 (*(volatile uint32_t*)0x30000000)
|
| 26 |
|
|
#define reg_mprj_globl_reg1 (*(volatile uint32_t*)0x30000004)
|
| 27 |
|
|
#define reg_mprj_globl_reg2 (*(volatile uint32_t*)0x30000008)
|
| 28 |
|
|
#define reg_mprj_globl_reg3 (*(volatile uint32_t*)0x3000000C)
|
| 29 |
|
|
#define reg_mprj_globl_reg4 (*(volatile uint32_t*)0x30000010)
|
| 30 |
|
|
#define reg_mprj_globl_reg5 (*(volatile uint32_t*)0x30000014)
|
| 31 |
|
|
#define reg_mprj_globl_reg6 (*(volatile uint32_t*)0x30000018)
|
| 32 |
|
|
#define reg_mprj_globl_reg7 (*(volatile uint32_t*)0x3000001C)
|
| 33 |
|
|
#define reg_mprj_globl_reg8 (*(volatile uint32_t*)0x30000020)
|
| 34 |
|
|
#define reg_mprj_globl_reg9 (*(volatile uint32_t*)0x30000024)
|
| 35 |
|
|
#define reg_mprj_globl_reg10 (*(volatile uint32_t*)0x30000028)
|
| 36 |
|
|
#define reg_mprj_globl_reg11 (*(volatile uint32_t*)0x3000002C)
|
| 37 |
|
|
#define reg_mprj_globl_reg12 (*(volatile uint32_t*)0x30000030)
|
| 38 |
|
|
#define reg_mprj_globl_reg13 (*(volatile uint32_t*)0x30000034)
|
| 39 |
|
|
#define reg_mprj_globl_reg14 (*(volatile uint32_t*)0x30000038)
|
| 40 |
|
|
#define reg_mprj_globl_reg15 (*(volatile uint32_t*)0x3000003C)
|
| 41 |
|
|
|
| 42 |
|
|
|
| 43 |
|
|
#define GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP 0x1C00
|
| 44 |
|
|
|
| 45 |
|
|
#define SC_SIM_OUTPORT (0xf0000000)
|
| 46 |
|
|
|
| 47 |
|
|
/*
|
| 48 |
|
|
RiscV Hello World test.
|
| 49 |
|
|
- Wake up the Risc V
|
| 50 |
|
|
- Boot from SPI Flash
|
| 51 |
|
|
- Riscv Write Hello World to SDRAM,
|
| 52 |
|
|
- External Wishbone read back validation the data
|
| 53 |
|
|
*/
|
| 54 |
|
|
int i = 0;
|
| 55 |
|
|
int clk = 0;
|
| 56 |
|
|
|
| 57 |
|
|
void main()
|
| 58 |
|
|
{
|
| 59 |
|
|
|
| 60 |
|
|
int bFail = 0;
|
| 61 |
|
|
/*
|
| 62 |
|
|
IO Control Registers
|
| 63 |
|
|
| DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
|
| 64 |
|
|
| 3-bits | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit |
|
| 65 |
|
|
Output: 0000_0110_0000_1110 (0x1808) = GPIO_MODE_USER_STD_OUTPUT
|
| 66 |
|
|
| DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
|
| 67 |
|
|
| 110 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
|
| 68 |
|
|
|
| 69 |
|
|
|
| 70 |
|
|
Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL
|
| 71 |
|
|
| DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
|
| 72 |
|
|
| 001 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
|
| 73 |
|
|
|
| 74 |
|
|
Input: 0000_0001_0000_1111 (0x1800) = GPIO_MODE_USER_STD_BIDIRECTIONAL
|
| 75 |
|
|
| DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
|
| 76 |
|
|
| 110 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 77 |
|
|
*/
|
| 78 |
|
|
|
| 79 |
|
|
/* Set up the housekeeping SPI to be connected internally so */
|
| 80 |
|
|
/* that external pin changes don't affect it. */
|
| 81 |
|
|
|
| 82 |
|
|
reg_spimaster_config = 0xa002; // Enable, prescaler = 2,
|
| 83 |
|
|
// connect to housekeeping SPI
|
| 84 |
|
|
|
| 85 |
|
|
// Connect the housekeeping SPI to the SPI master
|
| 86 |
|
|
// so that the CSB line is not left floating. This allows
|
| 87 |
|
|
// all of the GPIO pins to be used for user functions.
|
| 88 |
|
|
reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
|
| 89 |
|
|
reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
|
| 90 |
|
|
reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
|
| 91 |
|
|
reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
|
| 92 |
|
|
reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
|
| 93 |
|
|
reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
|
| 94 |
|
|
reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
|
| 95 |
|
|
reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
|
| 96 |
|
|
reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
|
| 97 |
|
|
reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
|
| 98 |
|
|
reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
|
| 99 |
|
|
reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
|
| 100 |
|
|
reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
|
| 101 |
|
|
reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
|
| 102 |
|
|
reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
|
| 103 |
|
|
reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
|
| 104 |
|
|
|
| 105 |
|
|
|
| 106 |
|
|
/* Apply configuration */
|
| 107 |
|
|
reg_mprj_xfer = 1;
|
| 108 |
|
|
while (reg_mprj_xfer == 1);
|
| 109 |
|
|
|
| 110 |
|
|
reg_la2_oenb = reg_la2_iena = 0xFFFFFFFF; // [95:64]
|
| 111 |
|
|
|
| 112 |
|
|
// Flag start of the test
|
| 113 |
|
|
reg_mprj_datal = 0xAB600000;
|
| 114 |
|
|
|
| 115 |
|
|
//-----------------------------------------------------
|
| 116 |
|
|
// Start of User Functionality and take over the GPIO Pins
|
| 117 |
|
|
// ------------------------------------------------------
|
| 118 |
|
|
// User block decide on the GPIO function
|
| 119 |
|
|
reg_mprj_io_37 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
|
| 120 |
|
|
reg_mprj_io_36 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
|
| 121 |
|
|
reg_mprj_io_35 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
|
| 122 |
|
|
reg_mprj_io_34 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
|
| 123 |
|
|
reg_mprj_io_33 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
|
| 124 |
|
|
reg_mprj_io_32 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
|
| 125 |
|
|
reg_mprj_io_31 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
|
| 126 |
|
|
reg_mprj_io_30 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
|
| 127 |
|
|
reg_mprj_io_29 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
|
| 128 |
|
|
reg_mprj_io_28 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
|
| 129 |
|
|
reg_mprj_io_27 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
|
| 130 |
|
|
reg_mprj_io_26 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
|
| 131 |
|
|
reg_mprj_io_25 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
|
| 132 |
|
|
reg_mprj_io_24 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
|
| 133 |
|
|
reg_mprj_io_23 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
|
| 134 |
|
|
reg_mprj_io_22 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
|
| 135 |
|
|
reg_mprj_io_21 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
|
| 136 |
|
|
reg_mprj_io_20 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
|
| 137 |
|
|
reg_mprj_io_19 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
|
| 138 |
|
|
reg_mprj_io_18 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
|
| 139 |
|
|
reg_mprj_io_17 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
|
| 140 |
|
|
reg_mprj_io_16 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
|
| 141 |
|
|
reg_mprj_io_15 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
|
| 142 |
|
|
reg_mprj_io_14 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
|
| 143 |
|
|
reg_mprj_io_13 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
|
| 144 |
|
|
reg_mprj_io_12 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
|
| 145 |
|
|
reg_mprj_io_11 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
|
| 146 |
|
|
reg_mprj_io_10 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
|
| 147 |
|
|
reg_mprj_io_9 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
|
| 148 |
|
|
reg_mprj_io_8 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
|
| 149 |
|
|
reg_mprj_io_7 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
|
| 150 |
|
|
reg_mprj_io_6 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
|
| 151 |
|
|
reg_mprj_io_5 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
|
| 152 |
|
|
reg_mprj_io_4 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
|
| 153 |
|
|
reg_mprj_io_3 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
|
| 154 |
|
|
reg_mprj_io_2 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
|
| 155 |
|
|
reg_mprj_io_1 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
|
| 156 |
|
|
reg_mprj_io_0 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
|
| 157 |
|
|
|
| 158 |
|
|
/* Apply configuration */
|
| 159 |
|
|
reg_mprj_xfer = 1;
|
| 160 |
|
|
while (reg_mprj_xfer == 1);
|
| 161 |
|
|
// SDRAM Config-2
|
| 162 |
|
|
reg_mprj_globl_reg5 = 0x100019E;
|
| 163 |
|
|
|
| 164 |
|
|
|
| 165 |
|
|
// SDRAM Config-1
|
| 166 |
|
|
reg_mprj_globl_reg4 = 0x2F172242;
|
| 167 |
|
|
|
| 168 |
|
|
// Wake Up CPU Core
|
| 169 |
|
|
reg_mprj_globl_reg0 = 0x07;
|
| 170 |
|
|
|
| 171 |
|
|
// Add some delay for user core to boot
|
| 172 |
|
|
for(i = 0; i < 40; i ++);
|
| 173 |
|
|
for(i = 0; i < 40; i ++);
|
| 174 |
|
|
|
| 175 |
|
|
if(reg_mprj_globl_reg6 != 0x11223344) bFail = 1;
|
| 176 |
|
|
if(reg_mprj_globl_reg7 != 0x22334455) bFail = 1;
|
| 177 |
|
|
if(reg_mprj_globl_reg8 != 0x33445566) bFail = 1;
|
| 178 |
|
|
if(reg_mprj_globl_reg9 != 0x44556677) bFail = 1;
|
| 179 |
|
|
if(reg_mprj_globl_reg10 != 0x55667788) bFail = 1;
|
| 180 |
|
|
if(reg_mprj_globl_reg11 != 0x66778899) bFail = 1;
|
| 181 |
|
|
|
| 182 |
|
|
|
| 183 |
|
|
if(bFail == 0) {
|
| 184 |
|
|
reg_mprj_datal = 0xAB610000;
|
| 185 |
|
|
} else {
|
| 186 |
|
|
reg_mprj_datal = 0xAB600000;
|
| 187 |
|
|
}
|
| 188 |
|
|
|
| 189 |
|
|
// Connect the housekeeping SPI to the SPI master
|
| 190 |
|
|
// so that the CSB line is not left floating. This allows
|
| 191 |
|
|
// all of the GPIO pins to be used for user functions.
|
| 192 |
|
|
reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
|
| 193 |
|
|
reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
|
| 194 |
|
|
reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
|
| 195 |
|
|
reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
|
| 196 |
|
|
reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
|
| 197 |
|
|
reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
|
| 198 |
|
|
reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
|
| 199 |
|
|
reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
|
| 200 |
|
|
reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
|
| 201 |
|
|
reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
|
| 202 |
|
|
reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
|
| 203 |
|
|
reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
|
| 204 |
|
|
reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
|
| 205 |
|
|
reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
|
| 206 |
|
|
reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
|
| 207 |
|
|
reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
|
| 208 |
|
|
|
| 209 |
|
|
|
| 210 |
|
|
/* Apply configuration */
|
| 211 |
|
|
reg_mprj_xfer = 1;
|
| 212 |
|
|
while (reg_mprj_xfer == 1);
|
| 213 |
|
|
}
|
