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dinesha |
//////////////////////////////////////////////////////////////////////
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//// ////
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//// Standalone User validation Test bench ////
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//// ////
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//// This file is part of the YIFive cores project ////
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//// http://www.opencores.org/cores/yifive/ ////
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//// ////
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//// Description ////
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// This is a standalone test bench to validate the ////
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// Digital core. ////
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// 1. User Risc core is booted using compiled code of ////
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// user_risc_boot.c ////
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// 2. User Risc core uses Serial Flash and SDRAM to boot ////
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// 3. After successful boot, Risc core will write signature ////
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// in to user register from 0x3000_0018 to 0x3000_002C ////
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// 4. Through the External Wishbone Interface we read back ////
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// and validate the user register to declared pass fail ////
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//// ////
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//// To Do: ////
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//// nothing ////
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//// ////
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//// Author(s): ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// ////
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//// Revision : ////
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//// 0.1 - 16th Feb 2021, Dinesh A ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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`default_nettype none
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`timescale 1 ns / 1 ps
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`include "uprj_netlists.v"
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`include "spiflash.v"
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`include "mt48lc8m8a2.v"
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module user_risc_boot_tb;
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reg clock;
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reg RSTB;
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reg power1, power2;
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reg power3, power4;
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reg wbd_ext_cyc_i; // strobe/request
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reg wbd_ext_stb_i; // strobe/request
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reg [31:0] wbd_ext_adr_i; // address
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reg wbd_ext_we_i; // write
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reg [31:0] wbd_ext_dat_i; // data output
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reg [3:0] wbd_ext_sel_i; // byte enable
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wire [31:0] wbd_ext_dat_o; // data input
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wire wbd_ext_ack_o; // acknowlegement
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wire wbd_ext_err_o; // error
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// User I/O
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wire [37:0] io_oeb;
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wire [37:0] io_out;
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wire [37:0] io_in;
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wire gpio;
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wire [37:0] mprj_io;
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wire [7:0] mprj_io_0;
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reg test_fail;
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reg [31:0] read_data;
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// External clock is used by default. Make this artificially fast for the
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// simulation. Normally this would be a slow clock and the digital PLL
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// would be the fast clock.
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always #12.5 clock <= (clock === 1'b0);
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initial begin
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clock = 0;
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wbd_ext_cyc_i ='h0; // strobe/request
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wbd_ext_stb_i ='h0; // strobe/request
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wbd_ext_adr_i ='h0; // address
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wbd_ext_we_i ='h0; // write
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wbd_ext_dat_i ='h0; // data output
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wbd_ext_sel_i ='h0; // byte enable
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end
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`ifdef WFDUMP
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initial begin
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$dumpfile("risc_boot.vcd");
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$dumpvars(0, user_risc_boot_tb);
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end
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`endif
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initial begin
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#200; // Wait for reset removal
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repeat (10) @(posedge clock);
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$display("Monitor: Standalone User Risc Boot Test Started");
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#1;
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//------------ SDRAM Config - 2
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wb_user_core_write('h3000_0014,'h100_019E);
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repeat (2) @(posedge clock);
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#1;
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//------------ SDRAM Config - 1
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wb_user_core_write('h3000_0010,'h2F17_2242);
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repeat (2) @(posedge clock);
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#1;
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// Remove all the reset
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wb_user_core_write('h3000_0000,'h7);
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// Repeat cycles of 1000 clock edges as needed to complete testbench
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repeat (30) begin
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repeat (1000) @(posedge clock);
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// $display("+1000 cycles");
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end
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$display("Monitor: Reading Back the expected value");
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// User RISC core expect to write these value in global
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// register, read back and decide on pass fail
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// 0x30000018 = 0x11223344;
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// 0x3000001C = 0x22334455;
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// 0x30000020 = 0x33445566;
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// 0x30000024 = 0x44556677;
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// 0x30000028 = 0x55667788;
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// 0x3000002C = 0x66778899;
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test_fail = 0;
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wb_user_core_read(32'h30000018,read_data);
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if(read_data != 32'h11223344) test_fail = 1;
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wb_user_core_read(32'h3000001C,read_data);
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if(read_data != 32'h22334455) test_fail = 1;
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wb_user_core_read(32'h30000020,read_data);
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if(read_data != 32'h33445566) test_fail = 1;
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wb_user_core_read(32'h30000024,read_data);
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if(read_data!= 32'h44556677) test_fail = 1;
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wb_user_core_read(32'h30000028,read_data);
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if(read_data!= 32'h55667788) test_fail = 1;
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wb_user_core_read(32'h3000002C,read_data) ;
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if(read_data != 32'h66778899) test_fail = 1;
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$display("###################################################");
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if(test_fail == 0) begin
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`ifdef GL
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$display("Monitor: Standalone User Risc Boot (GL) Passed");
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`else
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$display("Monitor: Standalone User Risc Boot (RTL) Passed");
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`endif
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end else begin
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`ifdef GL
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$display("Monitor: Standalone User Risc Boot (GL) Failed");
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`else
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$display("Monitor: Standalone User Risc Boot (RTL) Failed");
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`endif
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end
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$display("###################################################");
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$finish;
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end
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initial begin
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RSTB <= 1'b0;
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#100;
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RSTB <= 1'b1; // Release reset
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end
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digital_core u_core(
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`ifdef USE_POWER_PINS
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.vdda1(), // User area 1 3.3V supply
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.vdda2(), // User area 2 3.3V supply
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.vssa1(), // User area 1 analog ground
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.vssa2(), // User area 2 analog ground
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.vccd1(), // User area 1 1.8V supply
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.vccd2(), // User area 2 1.8v supply
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.vssd1(), // User area 1 digital ground
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.vssd2(), // User area 2 digital ground
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`endif
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.clk (clock), // System clock
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.rtc_clk (1'b1), // Real-time clock
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.rst_n (RSTB), // Regular Reset signal
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.wbd_ext_cyc_i (wbd_ext_cyc_i), // strobe/request
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.wbd_ext_stb_i (wbd_ext_stb_i), // strobe/request
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.wbd_ext_adr_i (wbd_ext_adr_i), // address
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.wbd_ext_we_i (wbd_ext_we_i), // write
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.wbd_ext_dat_i (wbd_ext_dat_i), // data output
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.wbd_ext_sel_i (wbd_ext_sel_i), // byte enable
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.wbd_ext_dat_o (wbd_ext_dat_o), // data input
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.wbd_ext_ack_o (wbd_ext_ack_o), // acknowlegement
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.wbd_ext_err_o (wbd_ext_err_o), // error
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// Logic Analyzer Signals
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.la_data_in ('0) ,
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.la_data_out (),
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.la_oenb ('0),
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// IOs
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.io_in (io_in) ,
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.io_out (io_out) ,
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.io_oeb (io_oeb) ,
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.irq ()
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);
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//------------------------------------------------------
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// Integrate the Serial flash with qurd support to
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// user core using the gpio pads
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// ----------------------------------------------------
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wire flash_clk = io_out[30];
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wire flash_csb = io_out[31];
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tri flash_io0 = (io_oeb[32]== 1'b0) ? io_out[32] : 1'bz;
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tri flash_io1 = (io_oeb[33]== 1'b0) ? io_out[33] : 1'bz;
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tri flash_io2 = (io_oeb[34]== 1'b0) ? io_out[34] : 1'bz;
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tri flash_io3 = (io_oeb[35]== 1'b0) ? io_out[35] : 1'bz;
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assign io_in[32] = flash_io0;
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assign io_in[33] = flash_io1;
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assign io_in[34] = flash_io2;
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assign io_in[35] = flash_io3;
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// Quard flash
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spiflash #(
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.FILENAME("user_risc_boot.hex")
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) u_user_spiflash (
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.csb(flash_csb),
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.clk(flash_clk),
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.io0(flash_io0),
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.io1(flash_io1),
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.io2(flash_io2),
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.io3(flash_io3)
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);
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//------------------------------------------------
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// Integrate the SDRAM 8 BIT Memory
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// -----------------------------------------------
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wire [7:0] Dq ; // SDRAM Read/Write Data Bus
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wire [0:0] sdr_dqm ; // SDRAM DATA Mask
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wire [1:0] sdr_ba ; // SDRAM Bank Select
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wire [12:0] sdr_addr ; // SDRAM ADRESS
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wire sdr_cs_n ; // chip select
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wire sdr_cke ; // clock gate
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wire sdr_ras_n ; // ras
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wire sdr_cas_n ; // cas
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wire sdr_we_n ; // write enable
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wire sdram_clk ;
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assign Dq[7:0] = (io_oeb[7:0] == 8'h0) ? io_out [7:0] : 8'hZZ;
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assign sdr_addr[12:0] = io_out [20:8] ;
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assign sdr_ba[1:0] = io_out [22:21] ;
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assign sdr_dqm[0] = io_out [23] ;
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assign sdr_we_n = io_out [24] ;
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assign sdr_cas_n = io_out [25] ;
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assign sdr_ras_n = io_out [26] ;
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assign sdr_cs_n = io_out [27] ;
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assign sdr_cke = io_out [28] ;
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assign sdram_clk = io_out [29] ;
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assign io_in[29] = sdram_clk;
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assign #(1) io_in[7:0] = Dq;
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// to fix the sdram interface timing issue
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wire #(1) sdram_clk_d = sdram_clk;
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// SDRAM 8bit
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mt48lc8m8a2 #(.data_bits(8)) u_sdram8 (
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.Dq (Dq ) ,
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.Addr (sdr_addr[11:0] ),
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.Ba (sdr_ba ),
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.Clk (sdram_clk_d ),
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.Cke (sdr_cke ),
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.Cs_n (sdr_cs_n ),
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.Ras_n (sdr_ras_n ),
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.Cas_n (sdr_cas_n ),
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.We_n (sdr_we_n ),
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.Dqm (sdr_dqm )
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);
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task wb_user_core_write;
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input [31:0] address;
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input [31:0] data;
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begin
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repeat (1) @(posedge clock);
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wbd_ext_adr_i =address; // address
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324 |
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wbd_ext_we_i ='h1; // write
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wbd_ext_dat_i =data; // data output
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326 |
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wbd_ext_sel_i ='hF; // byte enable
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327 |
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wbd_ext_cyc_i ='h1; // strobe/request
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328 |
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wbd_ext_stb_i ='h1; // strobe/request
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329 |
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wait(wbd_ext_ack_o == 1);
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repeat (1) @(posedge clock);
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331 |
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wbd_ext_cyc_i ='h0; // strobe/request
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332 |
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wbd_ext_stb_i ='h0; // strobe/request
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333 |
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wbd_ext_adr_i ='h0; // address
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334 |
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wbd_ext_we_i ='h0; // write
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335 |
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wbd_ext_dat_i ='h0; // data output
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336 |
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wbd_ext_sel_i ='h0; // byte enable
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337 |
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$display("DEBUG WB USER ACCESS WRITE Address : %x, Data : %x",address,data);
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338 |
|
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repeat (2) @(posedge clock);
|
339 |
|
|
end
|
340 |
|
|
endtask
|
341 |
|
|
|
342 |
|
|
task wb_user_core_read;
|
343 |
|
|
input [31:0] address;
|
344 |
|
|
output [31:0] data;
|
345 |
|
|
reg [31:0] data;
|
346 |
|
|
begin
|
347 |
|
|
repeat (1) @(posedge clock);
|
348 |
|
|
wbd_ext_adr_i =address; // address
|
349 |
|
|
wbd_ext_we_i ='h0; // write
|
350 |
|
|
wbd_ext_dat_i ='0; // data output
|
351 |
|
|
wbd_ext_sel_i ='hF; // byte enable
|
352 |
|
|
wbd_ext_cyc_i ='h1; // strobe/request
|
353 |
|
|
wbd_ext_stb_i ='h1; // strobe/request
|
354 |
|
|
wait(wbd_ext_ack_o == 1);
|
355 |
|
|
data = wbd_ext_dat_o;
|
356 |
|
|
repeat (1) @(posedge clock);
|
357 |
|
|
wbd_ext_cyc_i ='h0; // strobe/request
|
358 |
|
|
wbd_ext_stb_i ='h0; // strobe/request
|
359 |
|
|
wbd_ext_adr_i ='h0; // address
|
360 |
|
|
wbd_ext_we_i ='h0; // write
|
361 |
|
|
wbd_ext_dat_i ='h0; // data output
|
362 |
|
|
wbd_ext_sel_i ='h0; // byte enable
|
363 |
|
|
$display("DEBUG WB USER ACCESS READ Address : %x, Data : %x",address,data);
|
364 |
|
|
repeat (2) @(posedge clock);
|
365 |
|
|
end
|
366 |
|
|
endtask
|
367 |
|
|
|
368 |
|
|
|
369 |
|
|
|
370 |
|
|
|
371 |
|
|
////-----------------------------------------------------------------------------
|
372 |
|
|
//// RISC IMEM amd DMEM Monitoring TASK
|
373 |
|
|
////-----------------------------------------------------------------------------
|
374 |
|
|
//logic [`SCR1_DMEM_AWIDTH-1:0] core2imem_addr_o_r; // DMEM address
|
375 |
|
|
//logic [`SCR1_DMEM_AWIDTH-1:0] core2dmem_addr_o_r; // DMEM address
|
376 |
|
|
//logic core2dmem_cmd_o_r;
|
377 |
|
|
//
|
378 |
|
|
//`define RISC_CORE user_risc_boot_tb.u_core.u_riscv_top.i_core_top
|
379 |
|
|
//
|
380 |
|
|
//always@(posedge `RISC_CORE.clk) begin
|
381 |
|
|
// if(`RISC_CORE.imem2core_req_ack_i && `RISC_CORE.core2imem_req_o)
|
382 |
|
|
// core2imem_addr_o_r <= `RISC_CORE.core2imem_addr_o;
|
383 |
|
|
//
|
384 |
|
|
// if(`RISC_CORE.dmem2core_req_ack_i && `RISC_CORE.core2dmem_req_o) begin
|
385 |
|
|
// core2dmem_addr_o_r <= `RISC_CORE.core2dmem_addr_o;
|
386 |
|
|
// core2dmem_cmd_o_r <= `RISC_CORE.core2dmem_cmd_o;
|
387 |
|
|
// end
|
388 |
|
|
//
|
389 |
|
|
// if(`RISC_CORE.imem2core_resp_i !=0)
|
390 |
|
|
// $display("RISCV-DEBUG => IMEM ADDRESS: %x Read Data : %x Resonse: %x", core2imem_addr_o_r,`RISC_CORE.imem2core_rdata_i,`RISC_CORE.imem2core_resp_i);
|
391 |
|
|
// if((`RISC_CORE.dmem2core_resp_i !=0) && core2dmem_cmd_o_r)
|
392 |
|
|
// $display("RISCV-DEBUG => DMEM ADDRESS: %x Write Data: %x Resonse: %x", core2dmem_addr_o_r,`RISC_CORE.core2dmem_wdata_o,`RISC_CORE.dmem2core_resp_i);
|
393 |
|
|
// if((`RISC_CORE.dmem2core_resp_i !=0) && !core2dmem_cmd_o_r)
|
394 |
|
|
// $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", core2dmem_addr_o_r,`RISC_CORE.dmem2core_rdata_i,`RISC_CORE.dmem2core_resp_i);
|
395 |
|
|
//end
|
396 |
|
|
endmodule
|
397 |
|
|
`default_nettype wire
|