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dinesha |
//////////////////////////////////////////////////////////////////////
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//// ////
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//// Digital core ////
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//// ////
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//// This file is part of the YIFive cores project ////
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//// http://www.opencores.org/cores/yifive/ ////
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//// ////
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//// Description ////
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//// This is digital core and integrate all the main block ////
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//// here. Following block are integrated here ////
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//// 1. Risc V Core ////
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//// 2. SPI Master ////
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//// 3. Wishbone Cross Bar ////
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//// ////
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//// To Do: ////
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//// nothing ////
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//// ////
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//// Author(s): ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// ////
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//// Revision : ////
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//// 0.1 - 16th Feb 2021, Dinesh A ////
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//// Initial integration with Risc-V core + ////
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//// Wishbone Cross Bar + SPI Master ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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`include "scr1_arch_description.svh"
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`ifdef SCR1_IPIC_EN
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`include "scr1_ipic.svh"
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`endif // SCR1_IPIC_EN
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`include "sdrc_define.v"
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module digital_core
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#(
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parameter SDR_DW = 8, // SDR Data Width
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parameter SDR_BW = 1, // SDR Byte Width
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parameter WB_WIDTH = 32 // WB ADDRESS/DARA WIDTH
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) (
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input logic clk, // System clock
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input logic rtc_clk, // Real-time clock
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input logic pwrup_rst_n, // Power-Up Reset
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input logic cpu_rst_n, // CPU Reset (Core Reset)
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input logic rst_n, // Regular Reset signal
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`ifdef SCR1_DBG_EN
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output logic sys_rst_n_o, // External System Reset output
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// (for the processor cluster's components or
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// external SOC (could be useful in small
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// SCR-core-centric SOCs))
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output logic sys_rdc_qlfy_o, // System-to-External SOC Reset Domain Crossing Qualifier
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`endif // SCR1_DBG_EN
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// Fuses
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input logic [`SCR1_XLEN-1:0] fuse_mhartid, // Hart ID
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`ifdef SCR1_DBG_EN
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input logic [31:0] fuse_idcode, // TAPC IDCODE
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`endif // SCR1_DBG_EN
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// IRQ
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`ifdef SCR1_IPIC_EN
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input logic [SCR1_IRQ_LINES_NUM-1:0] irq_lines, // IRQ lines to IPIC
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`else // SCR1_IPIC_EN
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input logic ext_irq, // External IRQ input
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`endif // SCR1_IPIC_EN
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input logic soft_irq, // Software IRQ input
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`ifdef SCR1_DBG_EN
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// -- JTAG I/F
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input logic trst_n,
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input logic tck,
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input logic tms,
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input logic tdi,
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output logic tdo,
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output logic tdo_en,
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`endif // SCR1_DBG_EN
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input logic wbd_ext_stb_i, // strobe/request
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input logic [WB_WIDTH-1:0] wbd_ext_adr_i, // address
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input logic wbd_ext_we_i, // write
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input logic [WB_WIDTH-1:0] wbd_ext_dat_i, // data output
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input logic [3:0] wbd_ext_sel_i, // byte enable
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output logic [WB_WIDTH-1:0] wbd_ext_dat_o, // data input
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output logic wbd_ext_ack_o, // acknowlegement
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output logic wbd_ext_err_o, // error
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/* Interface to SDRAMs */
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output logic sdr_cke, // SDRAM CKE
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output logic sdr_cs_n, // SDRAM Chip Select
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output logic sdr_ras_n, // SDRAM ras
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output logic sdr_cas_n, // SDRAM cas
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output logic sdr_we_n, // SDRAM write enable
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output logic [SDR_BW-1:0] sdr_dqm, // SDRAM Data Mask
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output logic [1:0] sdr_ba, // SDRAM Bank Enable
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output logic [12:0] sdr_addr, // SDRAM Address
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input logic [SDR_DW-1:0] pad_sdr_din, // SDRA Data Input
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output logic [SDR_DW-1:0] sdr_dout, // SDRA Data output
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output logic [SDR_BW-1:0] sdr_den_n, // SDRAM Data Output enable
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input sdram_pad_clk,// Sdram clock loop back from pad
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// SPI Master I/F
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output logic spim_clk,
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output logic spim_csn0,
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output logic spim_csn1,
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output logic spim_csn2,
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output logic spim_csn3,
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output logic [1:0] spim_mode,
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input logic [3:0] spim_sdi, // SPI Master out
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output logic [3:0] spim_sdo, // SPI Master out
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output logic spi_en_tx // SPI Pad directional control
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//inout tri [3:0] spim_sdio // SPI Master in/out
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);
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//---------------------------------------------------
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// Local Parameter Declaration
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// --------------------------------------------------
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//---------------------------------------------------------------------
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// Wishbone Risc V Instruction Memory Interface
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//---------------------------------------------------------------------
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logic wbd_riscv_imem_stb_i; // strobe/request
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logic [WB_WIDTH-1:0] wbd_riscv_imem_adr_i; // address
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logic wbd_riscv_imem_we_i; // write
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logic [WB_WIDTH-1:0] wbd_riscv_imem_dat_i; // data output
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logic [3:0] wbd_riscv_imem_sel_i; // byte enable
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logic [WB_WIDTH-1:0] wbd_riscv_imem_dat_o; // data input
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logic wbd_riscv_imem_ack_o; // acknowlegement
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logic wbd_riscv_imem_err_o; // error
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//---------------------------------------------------------------------
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// RISC V Wishbone Data Memory Interface
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//---------------------------------------------------------------------
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logic wbd_riscv_dmem_stb_i; // strobe/request
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logic [WB_WIDTH-1:0] wbd_riscv_dmem_adr_i; // address
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logic wbd_riscv_dmem_we_i; // write
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logic [WB_WIDTH-1:0] wbd_riscv_dmem_dat_i; // data output
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logic [3:0] wbd_riscv_dmem_sel_i; // byte enable
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logic [WB_WIDTH-1:0] wbd_riscv_dmem_dat_o; // data input
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logic wbd_riscv_dmem_ack_o; // acknowlegement
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logic wbd_riscv_dmem_err_o; // error
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//---------------------------------------------------------------------
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// SPI Master Wishbone Interface
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//---------------------------------------------------------------------
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logic wbd_spim_stb_o; // strobe/request
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logic [WB_WIDTH-1:0] wbd_spim_adr_o; // address
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logic wbd_spim_we_o; // write
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logic [WB_WIDTH-1:0] wbd_spim_dat_o; // data output
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logic [3:0] wbd_spim_sel_o; // byte enable
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logic wbd_spim_cyc_o ;
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logic [WB_WIDTH-1:0] wbd_spim_dat_i; // data input
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logic wbd_spim_ack_i; // acknowlegement
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logic wbd_spim_err_i; // error
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//---------------------------------------------------------------------
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// SPI Master Wishbone Interface
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//---------------------------------------------------------------------
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logic wbd_sdram_stb_o ;
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logic [WB_WIDTH-1:0] wbd_sdram_addr_o;
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logic wbd_sdram_we_o ; // 1 - Write, 0 - Read
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logic [WB_WIDTH-1:0] wbd_sdram_dat_o ;
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logic [WB_WIDTH/8-1:0] wbd_sdram_sel_o ; // Byte enable
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logic wbd_sdram_cyc_o ;
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logic [2:0] wbd_sdram_cti_o ;
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logic [WB_WIDTH-1:0] wbd_sdram_dat_i ;
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logic wbd_sdram_ack_i ;
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//---------------------------------------------------------------------
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// Global Register Wishbone Interface
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//---------------------------------------------------------------------
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logic wbd_glbl_stb_o; // strobe/request
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logic [WB_WIDTH-1:0] wbd_glbl_addr_o; // address
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logic wbd_glbl_we_o; // write
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logic [WB_WIDTH-1:0] wbd_glbl_dat_o; // data output
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logic [3:0] wbd_glbl_sel_o; // byte enable
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logic wbd_glbl_cyc_o ;
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logic [WB_WIDTH-1:0] wbd_glbl_dat_i; // data input
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logic wbd_glbl_ack_i; // acknowlegement
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logic wbd_glbl_err_i; // error
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//------------------------------------------------
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// Configuration Parameter
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//------------------------------------------------
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logic [1:0] cfg_sdr_width ; // 2'b00 - 32 Bit SDR, 2'b01 - 16 Bit SDR, 2'b1x - 8 Bit
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logic [1:0] cfg_colbits ; // 2'b00 - 8 Bit column address,
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logic sdr_init_done ; // Indicate SDRAM Initialisation Done
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logic [3:0] cfg_sdr_tras_d ; // Active to precharge delay
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logic [3:0] cfg_sdr_trp_d ; // Precharge to active delay
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logic [3:0] cfg_sdr_trcd_d ; // Active to R/W delay
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logic cfg_sdr_en ; // Enable SDRAM controller
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logic [1:0] cfg_req_depth ; // Maximum Request accepted by SDRAM controller
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logic [12:0] cfg_sdr_mode_reg ;
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logic [2:0] cfg_sdr_cas ; // SDRAM CAS Latency
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logic [3:0] cfg_sdr_trcar_d ; // Auto-refresh period
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logic [3:0] cfg_sdr_twr_d ; // Write recovery delay
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logic [`SDR_RFSH_TIMER_W-1 : 0] cfg_sdr_rfsh ;
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logic [`SDR_RFSH_ROW_CNT_W -1 : 0] cfg_sdr_rfmax ;
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//-----------------------------------------------------------
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// SPI I/F
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// ////////////////////////////////////////////////////
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logic spim_sdo0 ; // SPI Master Data Out[0]
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logic spim_sdo1 ; // SPI Master Data Out[1]
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logic spim_sdo2 ; // SPI Master Data Out[2]
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logic spim_sdo3 ; // SPI Master Data Out[3]
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logic spim_sdi0 ; // SPI Master Data In[0]
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logic spim_sdi1 ; // SPI Master Data In[1]
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logic spim_sdi2 ; // SPI Master Data In[2]
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logic spim_sdi3 ; // SPI Master Data In[3]
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//`ifdef VERILATOR // Verilator has limited support for bi-di pad
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assign spim_sdi0 = spim_sdi[0];
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assign spim_sdi1 = spim_sdi[1];
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assign spim_sdi2 = spim_sdi[2];
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assign spim_sdi3 = spim_sdi[3];
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assign spim_sdo = {spim_sdo3,spim_sdo2,spim_sdo1,spim_sdo0};
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//`else
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// assign spim_sdi0 = spim_sdio[0];
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// assign spim_sdi1 = spim_sdio[1];
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// assign spim_sdi2 = spim_sdio[2];
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// assign spim_sdi3 = spim_sdio[3];
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//
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// assign spim_sdio[0] = (spi_en_tx) ? spim_sdo0 : 1'bz;
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// assign spim_sdio[1] = (spi_en_tx) ? spim_sdo1 : 1'bz;
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// assign spim_sdio[2] = (spi_en_tx) ? spim_sdo2 : 1'bz;
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// assign spim_sdio[3] = (spi_en_tx) ? spim_sdo3 : 1'bz;
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//
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//`endif
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//------------------------------------------------------------------------------
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// RISC V Core instance
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//------------------------------------------------------------------------------
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scr1_top_wb u_riscv_top (
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// Reset
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.pwrup_rst_n (pwrup_rst_n ),
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.rst_n (rst_n ),
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.cpu_rst_n (cpu_rst_n ),
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`ifdef SCR1_DBG_EN
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.sys_rst_n_o (sys_rst_n_o ),
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.sys_rdc_qlfy_o (sys_rdc_qlfy_o ),
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`endif // SCR1_DBG_EN
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// Clock
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.clk (clk ),
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.rtc_clk (rtc_clk ),
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// Fuses
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.fuse_mhartid (fuse_mhartid ),
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`ifdef SCR1_DBG_EN
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.fuse_idcode (`SCR1_TAP_IDCODE ),
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`endif // SCR1_DBG_EN
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// IRQ
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`ifdef SCR1_IPIC_EN
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.irq_lines ('0 ), // TODO - Interrupts
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`else // SCR1_IPIC_EN
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.ext_irq ('0 ), // TODO - Interrupts
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`endif // SCR1_IPIC_EN
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.soft_irq ('0 ), // TODO - Interrupts
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// DFT
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.test_mode (1'b0 ),
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.test_rst_n (1'b1 ),
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`ifdef SCR1_DBG_EN
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// JTAG
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.trst_n (trst_n ),
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.tck (tck ),
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.tms (tms ),
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.tdi (tdi ),
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.tdo (tdo ),
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.tdo_en (tdo_en ),
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`endif // SCR1_DBG_EN
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// Instruction memory interface
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.wbd_imem_stb_o (wbd_riscv_imem_stb_i ),
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.wbd_imem_adr_o (wbd_riscv_imem_adr_i ),
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.wbd_imem_we_o (wbd_riscv_imem_we_i ),
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.wbd_imem_dat_o (wbd_riscv_imem_dat_i ),
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.wbd_imem_sel_o (wbd_riscv_imem_sel_i ),
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.wbd_imem_dat_i (wbd_riscv_imem_dat_o ),
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.wbd_imem_ack_i (wbd_riscv_imem_ack_o ),
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|
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.wbd_imem_err_i (wbd_riscv_imem_err_o ),
|
308 |
|
|
|
309 |
|
|
// Data memory interface
|
310 |
|
|
.wbd_dmem_stb_o (wbd_riscv_dmem_stb_i ),
|
311 |
|
|
.wbd_dmem_adr_o (wbd_riscv_dmem_adr_i ),
|
312 |
|
|
.wbd_dmem_we_o (wbd_riscv_dmem_we_i ),
|
313 |
|
|
.wbd_dmem_dat_o (wbd_riscv_dmem_dat_i ),
|
314 |
|
|
.wbd_dmem_sel_o (wbd_riscv_dmem_sel_i ),
|
315 |
|
|
.wbd_dmem_dat_i (wbd_riscv_dmem_dat_o ),
|
316 |
|
|
.wbd_dmem_ack_i (wbd_riscv_dmem_ack_o ),
|
317 |
|
|
.wbd_dmem_err_i (wbd_riscv_dmem_err_o )
|
318 |
|
|
);
|
319 |
|
|
|
320 |
|
|
/*********************************************************
|
321 |
|
|
* SPI Master
|
322 |
|
|
* This is an implementation of an SPI master that is controlled via an AXI bus.
|
323 |
|
|
* It has FIFOs for transmitting and receiving data.
|
324 |
|
|
* It supports both the normal SPI mode and QPI mode with 4 data lines.
|
325 |
|
|
* *******************************************************/
|
326 |
|
|
|
327 |
|
|
spim_top
|
328 |
|
|
#(
|
329 |
|
|
`ifndef SYNTHESIS
|
330 |
|
|
.WB_WIDTH (WB_WIDTH)
|
331 |
|
|
`endif
|
332 |
|
|
) u_spi_master
|
333 |
|
|
(
|
334 |
|
|
.mclk (clk ),
|
335 |
|
|
.rst_n (rst_n ),
|
336 |
|
|
|
337 |
|
|
.wbd_stb_i (wbd_spim_stb_o ),
|
338 |
|
|
.wbd_adr_i (wbd_spim_adr_o ),
|
339 |
|
|
.wbd_we_i (wbd_spim_we_o ),
|
340 |
|
|
.wbd_dat_i (wbd_spim_dat_o ),
|
341 |
|
|
.wbd_sel_i (wbd_spim_sel_o ),
|
342 |
|
|
.wbd_dat_o (wbd_spim_dat_i ),
|
343 |
|
|
.wbd_ack_o (wbd_spim_ack_i ),
|
344 |
|
|
.wbd_err_o (wbd_spim_err_i ),
|
345 |
|
|
|
346 |
|
|
.events_o ( ), // TODO - Need to connect to intr ?
|
347 |
|
|
|
348 |
|
|
.spi_clk (spim_clk ),
|
349 |
|
|
.spi_csn0 (spim_csn0 ),
|
350 |
|
|
.spi_csn1 (spim_csn1 ),
|
351 |
|
|
.spi_csn2 (spim_csn2 ),
|
352 |
|
|
.spi_csn3 (spim_csn3 ),
|
353 |
|
|
.spi_mode (spim_mode ),
|
354 |
|
|
.spi_sdo0 (spim_sdo0 ),
|
355 |
|
|
.spi_sdo1 (spim_sdo1 ),
|
356 |
|
|
.spi_sdo2 (spim_sdo2 ),
|
357 |
|
|
.spi_sdo3 (spim_sdo3 ),
|
358 |
|
|
.spi_sdi0 (spim_sdi0 ),
|
359 |
|
|
.spi_sdi1 (spim_sdi1 ),
|
360 |
|
|
.spi_sdi2 (spim_sdi2 ),
|
361 |
|
|
.spi_sdi3 (spim_sdi3 ),
|
362 |
|
|
.spi_en_tx (spi_en_tx )
|
363 |
|
|
);
|
364 |
|
|
|
365 |
|
|
|
366 |
|
|
sdrc_top #(.APP_AW(WB_WIDTH),
|
367 |
|
|
.APP_DW(WB_WIDTH),
|
368 |
|
|
.APP_BW(4),
|
369 |
|
|
.SDR_DW(8),
|
370 |
|
|
.SDR_BW(1))
|
371 |
|
|
u_sdram_ctrl (
|
372 |
|
|
.cfg_sdr_width (cfg_sdr_width ),
|
373 |
|
|
.cfg_colbits (cfg_colbits ),
|
374 |
|
|
|
375 |
|
|
// WB bus
|
376 |
|
|
.wb_rst_i (rst_n ),
|
377 |
|
|
.wb_clk_i (clk ),
|
378 |
|
|
|
379 |
|
|
.wb_stb_i (wbd_sdram_stb_o ),
|
380 |
|
|
.wb_addr_i (wbd_sdram_addr_o ),
|
381 |
|
|
.wb_we_i (wbd_sdram_we_o ),
|
382 |
|
|
.wb_dat_i (wbd_sdram_dat_o ),
|
383 |
|
|
.wb_sel_i (wbd_sdram_sel_o ),
|
384 |
|
|
.wb_cyc_i (wbd_sdram_cyc_o ),
|
385 |
|
|
.wb_cti_i (wbd_sdram_cti_o ),
|
386 |
|
|
.wb_ack_o (wbd_sdram_ack_i ),
|
387 |
|
|
.wb_dat_o (wbd_sdram_dat_i ),
|
388 |
|
|
|
389 |
|
|
|
390 |
|
|
/* Interface to SDRAMs */
|
391 |
|
|
.sdram_clk (sdram_clk ),
|
392 |
|
|
.sdram_resetn (sdram_resetn ),
|
393 |
|
|
.sdr_cs_n (sdr_cs_n ),
|
394 |
|
|
.sdr_cke (sdr_cke ),
|
395 |
|
|
.sdr_ras_n (sdr_ras_n ),
|
396 |
|
|
.sdr_cas_n (sdr_cas_n ),
|
397 |
|
|
.sdr_we_n (sdr_we_n ),
|
398 |
|
|
.sdr_dqm (sdr_dqm ),
|
399 |
|
|
.sdr_ba (sdr_ba ),
|
400 |
|
|
.sdr_addr (sdr_addr ),
|
401 |
|
|
.pad_sdr_din (pad_sdr_din ),
|
402 |
|
|
.sdr_dout (sdr_dout ),
|
403 |
|
|
.sdr_den_n (sdr_den_n ),
|
404 |
|
|
.sdram_pad_clk (sdram_pad_clk ),
|
405 |
|
|
|
406 |
|
|
/* Parameters */
|
407 |
|
|
.sdr_init_done (sdr_init_done ),
|
408 |
|
|
.cfg_req_depth (cfg_req_depth ), //how many req. buffer should hold
|
409 |
|
|
.cfg_sdr_en (cfg_sdr_en ),
|
410 |
|
|
.cfg_sdr_mode_reg (cfg_sdr_mode_reg ),
|
411 |
|
|
.cfg_sdr_tras_d (cfg_sdr_tras_d ),
|
412 |
|
|
.cfg_sdr_trp_d (cfg_sdr_trp_d ),
|
413 |
|
|
.cfg_sdr_trcd_d (cfg_sdr_trcd_d ),
|
414 |
|
|
.cfg_sdr_cas (cfg_sdr_cas ),
|
415 |
|
|
.cfg_sdr_trcar_d (cfg_sdr_trcar_d ),
|
416 |
|
|
.cfg_sdr_twr_d (cfg_sdr_twr_d ),
|
417 |
|
|
.cfg_sdr_rfsh (cfg_sdr_rfsh ),
|
418 |
|
|
.cfg_sdr_rfmax (cfg_sdr_rfmax )
|
419 |
|
|
);
|
420 |
|
|
|
421 |
|
|
|
422 |
|
|
//------------------------------
|
423 |
|
|
// RISC Data Memory Map
|
424 |
|
|
// 0x0000_0000 to 0x0FFF_FFFF - SPI FLASH MEMORY
|
425 |
|
|
// 0x1000_0000 to 0x1000_00FF - SPI REGISTER
|
426 |
|
|
// 0x2000_0000 to 0x2FFF_FFFF - SDRAM
|
427 |
|
|
// 0x3000_0000 to 0x3000_00FF - GLOBAL REGISTER
|
428 |
|
|
//-----------------------------
|
429 |
|
|
//
|
430 |
|
|
wire [3:0] wbd_riscv_imem_tar_id = (wbd_riscv_imem_adr_i[31:28] == 4'b0000 ) ? 4'b0001 :
|
431 |
|
|
(wbd_riscv_imem_adr_i[31:28] == 4'b0001 ) ? 4'b0001 :
|
432 |
|
|
(wbd_riscv_imem_adr_i[31:28] == 4'b0010 ) ? 4'b0010 :
|
433 |
|
|
(wbd_riscv_imem_adr_i[31:28] == 4'b0011 ) ? 4'b0011 : 4'b0001;
|
434 |
|
|
|
435 |
|
|
wire [3:0] wbd_riscv_dmem_tar_id = (wbd_riscv_dmem_adr_i[31:28] == 4'b0000 ) ? 4'b0001 :
|
436 |
|
|
(wbd_riscv_dmem_adr_i[31:28] == 4'b0001 ) ? 4'b0001 :
|
437 |
|
|
(wbd_riscv_dmem_adr_i[31:28] == 4'b0010 ) ? 4'b0010 :
|
438 |
|
|
(wbd_riscv_dmem_adr_i[31:28] == 4'b0011 ) ? 4'b0011 : 4'b0001;
|
439 |
|
|
|
440 |
|
|
wire [3:0] wbd_ext_tar_id = (wbd_ext_adr_i[31:28] == 4'b0000 ) ? 4'b0001 :
|
441 |
|
|
(wbd_ext_adr_i[31:28] == 4'b0001 ) ? 4'b0001 :
|
442 |
|
|
(wbd_ext_adr_i[31:28] == 4'b0010 ) ? 4'b0010 :
|
443 |
|
|
(wbd_ext_adr_i[31:28] == 4'b0011 ) ? 4'b0011 : 4'b0001;
|
444 |
|
|
wb_crossbar #(
|
445 |
|
|
.WB_SLAVE(3),
|
446 |
|
|
.WB_MASTER(3),
|
447 |
|
|
.D_WD(32),
|
448 |
|
|
.BE_WD(4),
|
449 |
|
|
.ADR_WD(32),
|
450 |
|
|
.TAR_WD(4)
|
451 |
|
|
) u_wb_crossbar(
|
452 |
|
|
|
453 |
|
|
.rst_n (rst_n ),
|
454 |
|
|
.clk (clk ),
|
455 |
|
|
|
456 |
|
|
|
457 |
|
|
// Master Interface Signal
|
458 |
|
|
.wbd_taddr_master ({wbd_ext_tar_id,
|
459 |
|
|
wbd_riscv_dmem_tar_id,
|
460 |
|
|
wbd_riscv_imem_tar_id}),
|
461 |
|
|
.wbd_din_master ({wbd_ext_dat_i,
|
462 |
|
|
wbd_riscv_dmem_dat_i,
|
463 |
|
|
wbd_riscv_imem_dat_i}),
|
464 |
|
|
.wbd_dout_master ({wbd_ext_dat_o,
|
465 |
|
|
wbd_riscv_dmem_dat_o,
|
466 |
|
|
wbd_riscv_imem_dat_o}),
|
467 |
|
|
.wbd_adr_master ({wbd_ext_adr_i,
|
468 |
|
|
wbd_riscv_dmem_adr_i,
|
469 |
|
|
wbd_riscv_imem_adr_i} ),
|
470 |
|
|
.wbd_be_master ({wbd_ext_sel_i,
|
471 |
|
|
wbd_riscv_dmem_sel_i,
|
472 |
|
|
wbd_riscv_imem_sel_i}),
|
473 |
|
|
.wbd_we_master ({wbd_ext_we_i,
|
474 |
|
|
wbd_riscv_dmem_we_i,
|
475 |
|
|
wbd_riscv_imem_we_i}),
|
476 |
|
|
.wbd_ack_master ({wbd_ext_ack_o,
|
477 |
|
|
wbd_riscv_dmem_ack_o,
|
478 |
|
|
wbd_riscv_imem_ack_o}),
|
479 |
|
|
.wbd_stb_master ({wbd_ext_stb_i,
|
480 |
|
|
wbd_riscv_dmem_stb_i,
|
481 |
|
|
wbd_riscv_imem_stb_i}),
|
482 |
|
|
.wbd_cyc_master ({wbd_ext_stb_i,
|
483 |
|
|
wbd_riscv_dmem_stb_i,
|
484 |
|
|
wbd_riscv_imem_stb_i}),
|
485 |
|
|
.wbd_err_master ({wbd_ext_err_o,
|
486 |
|
|
wbd_riscv_dmem_err_o,
|
487 |
|
|
wbd_riscv_imem_err_o}),
|
488 |
|
|
.wbd_rty_master ( ),
|
489 |
|
|
|
490 |
|
|
// Slave Interface Signal
|
491 |
|
|
.wbd_din_slave ({wbd_glbl_dat_o,
|
492 |
|
|
wbd_sdram_dat_o,
|
493 |
|
|
wbd_spim_dat_o} ),
|
494 |
|
|
.wbd_dout_slave ({wbd_glbl_dat_i,
|
495 |
|
|
wbd_sdram_dat_i,
|
496 |
|
|
wbd_spim_dat_i} ),
|
497 |
|
|
.wbd_adr_slave ({wbd_glbl_addr_o,
|
498 |
|
|
wbd_sdram_addr_o,
|
499 |
|
|
wbd_spim_adr_o} ),
|
500 |
|
|
.wbd_be_slave ({wbd_glbl_sel_o,
|
501 |
|
|
wbd_sdram_sel_o,
|
502 |
|
|
wbd_spim_sel_o} ),
|
503 |
|
|
.wbd_we_slave ({wbd_glbl_we_o,
|
504 |
|
|
wbd_sdram_we_o,
|
505 |
|
|
wbd_spim_we_o} ),
|
506 |
|
|
.wbd_ack_slave ({wbd_glbl_ack_i,
|
507 |
|
|
wbd_sdram_ack_i,
|
508 |
|
|
wbd_spim_ack_i} ),
|
509 |
|
|
.wbd_stb_slave ({wbd_glbl_stb_o,
|
510 |
|
|
wbd_sdram_stb_o,
|
511 |
|
|
wbd_spim_stb_o} ),
|
512 |
|
|
.wbd_cyc_slave ({wbd_glbl_cyc_o,
|
513 |
|
|
wbd_sdram_cyc_o,
|
514 |
|
|
wbd_spim_cyc_o} ),
|
515 |
|
|
.wbd_err_slave (3'b0 ),
|
516 |
|
|
.wbd_rty_slave (3'b0 )
|
517 |
|
|
);
|
518 |
|
|
|
519 |
|
|
|
520 |
|
|
|
521 |
|
|
endmodule : digital_core
|