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dinesha |
/*********************************************************************
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SDRAM Controller Bank Controller
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This file is part of the sdram controller project
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http://www.opencores.org/cores/sdr_ctrl/
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Description:
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This module takes requests from sdrc_req_gen, checks for page hit/miss and
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issues precharge/activate commands and then passes the request to sdrc_xfr_ctl.
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To Do:
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nothing
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Author(s):
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- Dinesh Annayya, dinesha@opencores.org
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Version : 1.0 - 8th Jan 2012
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Copyright (C) 2000 Authors and OPENCORES.ORG
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This source file may be used and distributed without
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restriction provided that this copyright statement is not
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removed from the file and that any derivative work contains
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the original copyright notice and the associated disclaimer.
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This source file is free software; you can redistribute it
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and/or modify it under the terms of the GNU Lesser General
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Public License as published by the Free Software Foundation;
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either version 2.1 of the License, or (at your option) any
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later version.
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This source is distributed in the hope that it will be
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useful, but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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PURPOSE. See the GNU Lesser General Public License for more
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details.
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You should have received a copy of the GNU Lesser General
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Public License along with this source; if not, download it
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from http://www.opencores.org/lgpl.shtml
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*******************************************************************/
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`include "sdrc_define.v"
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module sdrc_bank_ctl (clk,
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reset_n,
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a2b_req_depth, // Number of requests we can buffer
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/* Req from req_gen */
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r2b_req, // request
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r2b_req_id, // ID
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r2b_start, // First chunk of burst
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r2b_last, // Last chunk of burst
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r2b_wrap,
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r2b_ba, // bank address
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r2b_raddr, // row address
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r2b_caddr, // col address
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r2b_len, // length
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r2b_write, // write request
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b2r_arb_ok, // OK to arbitrate for next xfr
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b2r_ack,
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/* Transfer request to xfr_ctl */
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b2x_idle, // All banks are idle
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b2x_req, // Request to xfr_ctl
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b2x_start, // first chunk of transfer
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b2x_last, // last chunk of transfer
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b2x_wrap,
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b2x_id, // Transfer ID
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b2x_ba, // bank address
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b2x_addr, // row/col address
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b2x_len, // transfer length
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b2x_cmd, // transfer command
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x2b_ack, // command accepted
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/* Status to/from xfr_ctl */
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b2x_tras_ok, // TRAS OK for all banks
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x2b_refresh, // We did a refresh
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x2b_pre_ok, // OK to do a precharge (per bank)
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x2b_act_ok, // OK to do an activate
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x2b_rdok, // OK to do a read
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x2b_wrok, // OK to do a write
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/* xfr msb address */
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xfr_bank_sel,
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sdr_req_norm_dma_last,
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/* SDRAM Timing */
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tras_delay, // Active to precharge delay
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trp_delay, // Precharge to active delay
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trcd_delay); // Active to R/W delay
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parameter SDR_DW = 16; // SDR Data Width
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parameter SDR_BW = 2; // SDR Byte Width
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input clk, reset_n;
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input [1:0] a2b_req_depth;
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/* Req from bank_ctl */
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input r2b_req, r2b_start, r2b_last,
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r2b_write, r2b_wrap;
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input [`SDR_REQ_ID_W-1:0] r2b_req_id;
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input [1:0] r2b_ba;
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input [12:0] r2b_raddr;
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input [12:0] r2b_caddr;
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input [`REQ_BW-1:0] r2b_len;
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output b2r_arb_ok, b2r_ack;
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input sdr_req_norm_dma_last;
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/* Req to xfr_ctl */
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output b2x_idle, b2x_req, b2x_start, b2x_last,
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b2x_tras_ok, b2x_wrap;
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output [`SDR_REQ_ID_W-1:0] b2x_id;
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output [1:0] b2x_ba;
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output [12:0] b2x_addr;
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output [`REQ_BW-1:0] b2x_len;
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output [1:0] b2x_cmd;
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input x2b_ack;
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/* Status from xfr_ctl */
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input [3:0] x2b_pre_ok;
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input x2b_refresh, x2b_act_ok, x2b_rdok,
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x2b_wrok;
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input [3:0] tras_delay, trp_delay, trcd_delay;
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input [1:0] xfr_bank_sel;
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/****************************************************************************/
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// Internal Nets
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wire [3:0] r2i_req, i2r_ack, i2x_req,
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i2x_start, i2x_last, i2x_wrap, tras_ok;
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wire [12:0] i2x_addr0, i2x_addr1, i2x_addr2, i2x_addr3;
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wire [`REQ_BW-1:0] i2x_len0, i2x_len1, i2x_len2, i2x_len3;
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wire [1:0] i2x_cmd0, i2x_cmd1, i2x_cmd2, i2x_cmd3;
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wire [`SDR_REQ_ID_W-1:0] i2x_id0, i2x_id1, i2x_id2, i2x_id3;
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reg b2x_req;
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wire b2x_idle, b2x_start, b2x_last, b2x_wrap;
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wire [`SDR_REQ_ID_W-1:0] b2x_id;
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wire [12:0] b2x_addr;
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wire [`REQ_BW-1:0] b2x_len;
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wire [1:0] b2x_cmd;
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wire [3:0] x2i_ack;
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reg [1:0] b2x_ba;
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reg [`SDR_REQ_ID_W-1:0] curr_id;
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wire [1:0] xfr_ba;
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wire xfr_ba_last;
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wire [3:0] xfr_ok;
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// This 8 bit register stores the bank addresses for upto 4 requests.
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reg [7:0] rank_ba;
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reg [3:0] rank_ba_last;
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// This 3 bit counter counts the number of requests we have
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// buffered so far, legal values are 0, 1, 2, 3, or 4.
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reg [2:0] rank_cnt;
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wire [3:0] rank_req, rank_wr_sel;
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wire rank_fifo_wr, rank_fifo_rd;
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wire rank_fifo_full, rank_fifo_mt;
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wire [12:0] bank0_row, bank1_row, bank2_row, bank3_row;
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assign b2x_tras_ok = &tras_ok;
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// Distribute the request from req_gen
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assign r2i_req[0] = (r2b_ba == 2'b00) ? r2b_req & ~rank_fifo_full : 1'b0;
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assign r2i_req[1] = (r2b_ba == 2'b01) ? r2b_req & ~rank_fifo_full : 1'b0;
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assign r2i_req[2] = (r2b_ba == 2'b10) ? r2b_req & ~rank_fifo_full : 1'b0;
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assign r2i_req[3] = (r2b_ba == 2'b11) ? r2b_req & ~rank_fifo_full : 1'b0;
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/******************
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Modified the Better FPGA Timing Purpose
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assign b2r_ack = (r2b_ba == 2'b00) ? i2r_ack[0] :
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(r2b_ba == 2'b01) ? i2r_ack[1] :
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(r2b_ba == 2'b10) ? i2r_ack[2] :
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(r2b_ba == 2'b11) ? i2r_ack[3] : 1'b0;
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********************/
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// Assumption: Only one Ack Will be asserted at a time.
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assign b2r_ack =|i2r_ack;
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assign b2r_arb_ok = ~rank_fifo_full;
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// Put the requests from the 4 bank_fsms into a 4 deep shift
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// register file. The earliest request is prioritized over the
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// later requests. Also the number of requests we are allowed to
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// buffer is limited by a 2 bit external input
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// Mux the req/cmd to xfr_ctl. Allow RD/WR commands from the request in
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// rank0, allow only PR/ACT commands from the requests in other ranks
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// If the rank_fifo is empty, send the request from the bank addressed by
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// r2b_ba
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// In FPGA Mode, to improve the timing, also send the rank_ba
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assign xfr_ba = (`TARGET_DESIGN == `FPGA) ? rank_ba[1:0]:
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((rank_fifo_mt) ? r2b_ba : rank_ba[1:0]);
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assign xfr_ba_last = (`TARGET_DESIGN == `FPGA) ? rank_ba_last[0]:
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((rank_fifo_mt) ? sdr_req_norm_dma_last : rank_ba_last[0]);
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assign rank_req[0] = i2x_req[xfr_ba]; // each rank generates requests
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assign rank_req[1] = (rank_cnt < 3'h2) ? 1'b0 :
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(rank_ba[3:2] == 2'b00) ? i2x_req[0] & ~i2x_cmd0[1] :
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(rank_ba[3:2] == 2'b01) ? i2x_req[1] & ~i2x_cmd1[1] :
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(rank_ba[3:2] == 2'b10) ? i2x_req[2] & ~i2x_cmd2[1] :
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i2x_req[3] & ~i2x_cmd3[1];
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assign rank_req[2] = (rank_cnt < 3'h3) ? 1'b0 :
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(rank_ba[5:4] == 2'b00) ? i2x_req[0] & ~i2x_cmd0[1] :
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(rank_ba[5:4] == 2'b01) ? i2x_req[1] & ~i2x_cmd1[1] :
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(rank_ba[5:4] == 2'b10) ? i2x_req[2] & ~i2x_cmd2[1] :
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i2x_req[3] & ~i2x_cmd3[1];
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assign rank_req[3] = (rank_cnt < 3'h4) ? 1'b0 :
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(rank_ba[7:6] == 2'b00) ? i2x_req[0] & ~i2x_cmd0[1] :
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(rank_ba[7:6] == 2'b01) ? i2x_req[1] & ~i2x_cmd1[1] :
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(rank_ba[7:6] == 2'b10) ? i2x_req[2] & ~i2x_cmd2[1] :
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i2x_req[3] & ~i2x_cmd3[1];
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always @ (*) begin
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b2x_req = 1'b0;
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b2x_ba = xfr_ba;
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if(`TARGET_DESIGN == `ASIC) begin // Support Multiple Rank request only on ASIC
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if (rank_req[0]) begin
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b2x_req = 1'b1;
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b2x_ba = xfr_ba;
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end // if (rank_req[0])
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else if (rank_req[1]) begin
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b2x_req = 1'b1;
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b2x_ba = rank_ba[3:2];
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end // if (rank_req[1])
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else if (rank_req[2]) begin
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b2x_req = 1'b1;
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b2x_ba = rank_ba[5:4];
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end // if (rank_req[2])
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else if (rank_req[3]) begin
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b2x_req = 1'b1;
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b2x_ba = rank_ba[7:6];
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end // if (rank_req[3])
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end else begin // If FPGA
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if (rank_req[0]) begin
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b2x_req = 1'b1;
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end
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end
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end // always @ (rank_req or rank_fifo_mt or r2b_ba or rank_ba)
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assign b2x_idle = rank_fifo_mt;
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assign b2x_start = i2x_start[b2x_ba];
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assign b2x_last = i2x_last[b2x_ba];
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assign b2x_wrap = i2x_wrap[b2x_ba];
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assign b2x_addr = (b2x_ba == 2'b11) ? i2x_addr3 :
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(b2x_ba == 2'b10) ? i2x_addr2 :
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(b2x_ba == 2'b01) ? i2x_addr1 : i2x_addr0;
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assign b2x_len = (b2x_ba == 2'b11) ? i2x_len3 :
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(b2x_ba == 2'b10) ? i2x_len2 :
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(b2x_ba == 2'b01) ? i2x_len1 : i2x_len0;
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assign b2x_cmd = (b2x_ba == 2'b11) ? i2x_cmd3 :
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(b2x_ba == 2'b10) ? i2x_cmd2 :
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(b2x_ba == 2'b01) ? i2x_cmd1 : i2x_cmd0;
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assign b2x_id = (b2x_ba == 2'b11) ? i2x_id3 :
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(b2x_ba == 2'b10) ? i2x_id2 :
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(b2x_ba == 2'b01) ? i2x_id1 : i2x_id0;
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assign x2i_ack[0] = (b2x_ba == 2'b00) ? x2b_ack : 1'b0;
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assign x2i_ack[1] = (b2x_ba == 2'b01) ? x2b_ack : 1'b0;
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assign x2i_ack[2] = (b2x_ba == 2'b10) ? x2b_ack : 1'b0;
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assign x2i_ack[3] = (b2x_ba == 2'b11) ? x2b_ack : 1'b0;
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// Rank Fifo
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// On a write write to selected rank and increment rank_cnt
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// On a read shift rank_ba right 2 bits and decrement rank_cnt
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assign rank_fifo_wr = b2r_ack;
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assign rank_fifo_rd = b2x_req & b2x_cmd[1] & x2b_ack;
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assign rank_wr_sel[0] = (rank_cnt == 3'h0) ? rank_fifo_wr :
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(rank_cnt == 3'h1) ? rank_fifo_wr & rank_fifo_rd :
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| 292 |
|
|
1'b0;
|
| 293 |
|
|
|
| 294 |
|
|
assign rank_wr_sel[1] = (rank_cnt == 3'h1) ? rank_fifo_wr & ~rank_fifo_rd :
|
| 295 |
|
|
(rank_cnt == 3'h2) ? rank_fifo_wr & rank_fifo_rd :
|
| 296 |
|
|
1'b0;
|
| 297 |
|
|
|
| 298 |
|
|
assign rank_wr_sel[2] = (rank_cnt == 3'h2) ? rank_fifo_wr & ~rank_fifo_rd :
|
| 299 |
|
|
(rank_cnt == 3'h3) ? rank_fifo_wr & rank_fifo_rd :
|
| 300 |
|
|
1'b0;
|
| 301 |
|
|
|
| 302 |
|
|
assign rank_wr_sel[3] = (rank_cnt == 3'h3) ? rank_fifo_wr & ~rank_fifo_rd :
|
| 303 |
|
|
(rank_cnt == 3'h4) ? rank_fifo_wr & rank_fifo_rd :
|
| 304 |
|
|
1'b0;
|
| 305 |
|
|
|
| 306 |
|
|
assign rank_fifo_mt = (rank_cnt == 3'b0) ? 1'b1 : 1'b0;
|
| 307 |
|
|
|
| 308 |
|
|
assign rank_fifo_full = (rank_cnt[2]) ? 1'b1 :
|
| 309 |
|
|
(rank_cnt[1:0] == a2b_req_depth) ? 1'b1 : 1'b0;
|
| 310 |
|
|
|
| 311 |
|
|
// FIFO Check
|
| 312 |
|
|
|
| 313 |
|
|
// synopsys translate_off
|
| 314 |
|
|
|
| 315 |
|
|
always @ (posedge clk) begin
|
| 316 |
|
|
|
| 317 |
|
|
if (~rank_fifo_wr & rank_fifo_rd && rank_cnt == 3'h0) begin
|
| 318 |
|
|
$display ("%t: %m: ERROR!!! Read from empty Fifo", $time);
|
| 319 |
|
|
$stop;
|
| 320 |
|
|
end // if (rank_fifo_rd && rank_cnt == 3'h0)
|
| 321 |
|
|
|
| 322 |
|
|
if (rank_fifo_wr && ~rank_fifo_rd && rank_cnt == 3'h4) begin
|
| 323 |
|
|
$display ("%t: %m: ERROR!!! Write to full Fifo", $time);
|
| 324 |
|
|
$stop;
|
| 325 |
|
|
end // if (rank_fifo_wr && ~rank_fifo_rd && rank_cnt == 3'h4)
|
| 326 |
|
|
|
| 327 |
|
|
end // always @ (posedge clk)
|
| 328 |
|
|
|
| 329 |
|
|
// synopsys translate_on
|
| 330 |
|
|
|
| 331 |
|
|
always @ (posedge clk)
|
| 332 |
|
|
if (~reset_n) begin
|
| 333 |
|
|
rank_cnt <= 3'b0;
|
| 334 |
|
|
rank_ba <= 8'b0;
|
| 335 |
|
|
rank_ba_last <= 4'b0;
|
| 336 |
|
|
|
| 337 |
|
|
end // if (~reset_n)
|
| 338 |
|
|
else begin
|
| 339 |
|
|
|
| 340 |
|
|
rank_cnt <= (rank_fifo_wr & ~rank_fifo_rd) ? rank_cnt + 3'b1 :
|
| 341 |
|
|
(~rank_fifo_wr & rank_fifo_rd) ? rank_cnt - 3'b1 :
|
| 342 |
|
|
rank_cnt;
|
| 343 |
|
|
|
| 344 |
|
|
rank_ba[1:0] <= (rank_wr_sel[0]) ? r2b_ba :
|
| 345 |
|
|
(rank_fifo_rd) ? rank_ba[3:2] : rank_ba[1:0];
|
| 346 |
|
|
|
| 347 |
|
|
rank_ba[3:2] <= (rank_wr_sel[1]) ? r2b_ba :
|
| 348 |
|
|
(rank_fifo_rd) ? rank_ba[5:4] : rank_ba[3:2];
|
| 349 |
|
|
|
| 350 |
|
|
rank_ba[5:4] <= (rank_wr_sel[2]) ? r2b_ba :
|
| 351 |
|
|
(rank_fifo_rd) ? rank_ba[7:6] : rank_ba[5:4];
|
| 352 |
|
|
|
| 353 |
|
|
rank_ba[7:6] <= (rank_wr_sel[3]) ? r2b_ba :
|
| 354 |
|
|
(rank_fifo_rd) ? 2'b00 : rank_ba[7:6];
|
| 355 |
|
|
|
| 356 |
|
|
if(`TARGET_DESIGN == `ASIC) begin // This Logic is implemented for ASIC Only
|
| 357 |
|
|
// Note: Currenly top-level does not generate the
|
| 358 |
|
|
// sdr_req_norm_dma_last signal and can be tied zero at top-level
|
| 359 |
|
|
rank_ba_last[0] <= (rank_wr_sel[0]) ? sdr_req_norm_dma_last :
|
| 360 |
|
|
(rank_fifo_rd) ? rank_ba_last[1] : rank_ba_last[0];
|
| 361 |
|
|
|
| 362 |
|
|
rank_ba_last[1] <= (rank_wr_sel[1]) ? sdr_req_norm_dma_last :
|
| 363 |
|
|
(rank_fifo_rd) ? rank_ba_last[2] : rank_ba_last[1];
|
| 364 |
|
|
|
| 365 |
|
|
rank_ba_last[2] <= (rank_wr_sel[2]) ? sdr_req_norm_dma_last :
|
| 366 |
|
|
(rank_fifo_rd) ? rank_ba_last[3] : rank_ba_last[2];
|
| 367 |
|
|
|
| 368 |
|
|
rank_ba_last[3] <= (rank_wr_sel[3]) ? sdr_req_norm_dma_last :
|
| 369 |
|
|
(rank_fifo_rd) ? 1'b0 : rank_ba_last[3];
|
| 370 |
|
|
end
|
| 371 |
|
|
|
| 372 |
|
|
end // else: !if(~reset_n)
|
| 373 |
|
|
|
| 374 |
|
|
assign xfr_ok[0] = (xfr_ba == 2'b00) ? 1'b1 : 1'b0;
|
| 375 |
|
|
assign xfr_ok[1] = (xfr_ba == 2'b01) ? 1'b1 : 1'b0;
|
| 376 |
|
|
assign xfr_ok[2] = (xfr_ba == 2'b10) ? 1'b1 : 1'b0;
|
| 377 |
|
|
assign xfr_ok[3] = (xfr_ba == 2'b11) ? 1'b1 : 1'b0;
|
| 378 |
|
|
|
| 379 |
|
|
/****************************************************************************/
|
| 380 |
|
|
// Instantiate Bank Ctl FSM 0
|
| 381 |
|
|
|
| 382 |
|
|
sdrc_bank_fsm bank0_fsm (.clk (clk),
|
| 383 |
|
|
.reset_n (reset_n),
|
| 384 |
|
|
|
| 385 |
|
|
/* Req from req_gen */
|
| 386 |
|
|
.r2b_req (r2i_req[0]),
|
| 387 |
|
|
.r2b_req_id (r2b_req_id),
|
| 388 |
|
|
.r2b_start (r2b_start),
|
| 389 |
|
|
.r2b_last (r2b_last),
|
| 390 |
|
|
.r2b_wrap (r2b_wrap),
|
| 391 |
|
|
.r2b_raddr (r2b_raddr),
|
| 392 |
|
|
.r2b_caddr (r2b_caddr),
|
| 393 |
|
|
.r2b_len (r2b_len),
|
| 394 |
|
|
.r2b_write (r2b_write),
|
| 395 |
|
|
.b2r_ack (i2r_ack[0]),
|
| 396 |
|
|
.sdr_dma_last(rank_ba_last[0]),
|
| 397 |
|
|
|
| 398 |
|
|
/* Transfer request to xfr_ctl */
|
| 399 |
|
|
.b2x_req (i2x_req[0]),
|
| 400 |
|
|
.b2x_start (i2x_start[0]),
|
| 401 |
|
|
.b2x_last (i2x_last[0]),
|
| 402 |
|
|
.b2x_wrap (i2x_wrap[0]),
|
| 403 |
|
|
.b2x_id (i2x_id0),
|
| 404 |
|
|
.b2x_addr (i2x_addr0),
|
| 405 |
|
|
.b2x_len (i2x_len0),
|
| 406 |
|
|
.b2x_cmd (i2x_cmd0),
|
| 407 |
|
|
.x2b_ack (x2i_ack[0]),
|
| 408 |
|
|
|
| 409 |
|
|
/* Status to/from xfr_ctl */
|
| 410 |
|
|
.tras_ok (tras_ok[0]),
|
| 411 |
|
|
.xfr_ok (xfr_ok[0]),
|
| 412 |
|
|
.x2b_refresh (x2b_refresh),
|
| 413 |
|
|
.x2b_pre_ok (x2b_pre_ok[0]),
|
| 414 |
|
|
.x2b_act_ok (x2b_act_ok),
|
| 415 |
|
|
.x2b_rdok (x2b_rdok),
|
| 416 |
|
|
.x2b_wrok (x2b_wrok),
|
| 417 |
|
|
|
| 418 |
|
|
.bank_row(bank0_row),
|
| 419 |
|
|
|
| 420 |
|
|
/* SDRAM Timing */
|
| 421 |
|
|
.tras_delay (tras_delay),
|
| 422 |
|
|
.trp_delay (trp_delay),
|
| 423 |
|
|
.trcd_delay (trcd_delay));
|
| 424 |
|
|
|
| 425 |
|
|
/****************************************************************************/
|
| 426 |
|
|
// Instantiate Bank Ctl FSM 1
|
| 427 |
|
|
|
| 428 |
|
|
sdrc_bank_fsm bank1_fsm (.clk (clk),
|
| 429 |
|
|
.reset_n (reset_n),
|
| 430 |
|
|
|
| 431 |
|
|
/* Req from req_gen */
|
| 432 |
|
|
.r2b_req (r2i_req[1]),
|
| 433 |
|
|
.r2b_req_id (r2b_req_id),
|
| 434 |
|
|
.r2b_start (r2b_start),
|
| 435 |
|
|
.r2b_last (r2b_last),
|
| 436 |
|
|
.r2b_wrap (r2b_wrap),
|
| 437 |
|
|
.r2b_raddr (r2b_raddr),
|
| 438 |
|
|
.r2b_caddr (r2b_caddr),
|
| 439 |
|
|
.r2b_len (r2b_len),
|
| 440 |
|
|
.r2b_write (r2b_write),
|
| 441 |
|
|
.b2r_ack (i2r_ack[1]),
|
| 442 |
|
|
.sdr_dma_last(rank_ba_last[1]),
|
| 443 |
|
|
|
| 444 |
|
|
/* Transfer request to xfr_ctl */
|
| 445 |
|
|
.b2x_req (i2x_req[1]),
|
| 446 |
|
|
.b2x_start (i2x_start[1]),
|
| 447 |
|
|
.b2x_last (i2x_last[1]),
|
| 448 |
|
|
.b2x_wrap (i2x_wrap[1]),
|
| 449 |
|
|
.b2x_id (i2x_id1),
|
| 450 |
|
|
.b2x_addr (i2x_addr1),
|
| 451 |
|
|
.b2x_len (i2x_len1),
|
| 452 |
|
|
.b2x_cmd (i2x_cmd1),
|
| 453 |
|
|
.x2b_ack (x2i_ack[1]),
|
| 454 |
|
|
|
| 455 |
|
|
/* Status to/from xfr_ctl */
|
| 456 |
|
|
.tras_ok (tras_ok[1]),
|
| 457 |
|
|
.xfr_ok (xfr_ok[1]),
|
| 458 |
|
|
.x2b_refresh (x2b_refresh),
|
| 459 |
|
|
.x2b_pre_ok (x2b_pre_ok[1]),
|
| 460 |
|
|
.x2b_act_ok (x2b_act_ok),
|
| 461 |
|
|
.x2b_rdok (x2b_rdok),
|
| 462 |
|
|
.x2b_wrok (x2b_wrok),
|
| 463 |
|
|
|
| 464 |
|
|
.bank_row(bank1_row),
|
| 465 |
|
|
|
| 466 |
|
|
/* SDRAM Timing */
|
| 467 |
|
|
.tras_delay (tras_delay),
|
| 468 |
|
|
.trp_delay (trp_delay),
|
| 469 |
|
|
.trcd_delay (trcd_delay));
|
| 470 |
|
|
|
| 471 |
|
|
/****************************************************************************/
|
| 472 |
|
|
// Instantiate Bank Ctl FSM 2
|
| 473 |
|
|
|
| 474 |
|
|
sdrc_bank_fsm bank2_fsm (.clk (clk),
|
| 475 |
|
|
.reset_n (reset_n),
|
| 476 |
|
|
|
| 477 |
|
|
/* Req from req_gen */
|
| 478 |
|
|
.r2b_req (r2i_req[2]),
|
| 479 |
|
|
.r2b_req_id (r2b_req_id),
|
| 480 |
|
|
.r2b_start (r2b_start),
|
| 481 |
|
|
.r2b_last (r2b_last),
|
| 482 |
|
|
.r2b_wrap (r2b_wrap),
|
| 483 |
|
|
.r2b_raddr (r2b_raddr),
|
| 484 |
|
|
.r2b_caddr (r2b_caddr),
|
| 485 |
|
|
.r2b_len (r2b_len),
|
| 486 |
|
|
.r2b_write (r2b_write),
|
| 487 |
|
|
.b2r_ack (i2r_ack[2]),
|
| 488 |
|
|
.sdr_dma_last(rank_ba_last[2]),
|
| 489 |
|
|
|
| 490 |
|
|
/* Transfer request to xfr_ctl */
|
| 491 |
|
|
.b2x_req (i2x_req[2]),
|
| 492 |
|
|
.b2x_start (i2x_start[2]),
|
| 493 |
|
|
.b2x_last (i2x_last[2]),
|
| 494 |
|
|
.b2x_wrap (i2x_wrap[2]),
|
| 495 |
|
|
.b2x_id (i2x_id2),
|
| 496 |
|
|
.b2x_addr (i2x_addr2),
|
| 497 |
|
|
.b2x_len (i2x_len2),
|
| 498 |
|
|
.b2x_cmd (i2x_cmd2),
|
| 499 |
|
|
.x2b_ack (x2i_ack[2]),
|
| 500 |
|
|
|
| 501 |
|
|
/* Status to/from xfr_ctl */
|
| 502 |
|
|
.tras_ok (tras_ok[2]),
|
| 503 |
|
|
.xfr_ok (xfr_ok[2]),
|
| 504 |
|
|
.x2b_refresh (x2b_refresh),
|
| 505 |
|
|
.x2b_pre_ok (x2b_pre_ok[2]),
|
| 506 |
|
|
.x2b_act_ok (x2b_act_ok),
|
| 507 |
|
|
.x2b_rdok (x2b_rdok),
|
| 508 |
|
|
.x2b_wrok (x2b_wrok),
|
| 509 |
|
|
|
| 510 |
|
|
.bank_row(bank2_row),
|
| 511 |
|
|
|
| 512 |
|
|
/* SDRAM Timing */
|
| 513 |
|
|
.tras_delay (tras_delay),
|
| 514 |
|
|
.trp_delay (trp_delay),
|
| 515 |
|
|
.trcd_delay (trcd_delay));
|
| 516 |
|
|
|
| 517 |
|
|
/****************************************************************************/
|
| 518 |
|
|
// Instantiate Bank Ctl FSM 3
|
| 519 |
|
|
|
| 520 |
|
|
sdrc_bank_fsm bank3_fsm (.clk (clk),
|
| 521 |
|
|
.reset_n (reset_n),
|
| 522 |
|
|
|
| 523 |
|
|
/* Req from req_gen */
|
| 524 |
|
|
.r2b_req (r2i_req[3]),
|
| 525 |
|
|
.r2b_req_id (r2b_req_id),
|
| 526 |
|
|
.r2b_start (r2b_start),
|
| 527 |
|
|
.r2b_last (r2b_last),
|
| 528 |
|
|
.r2b_wrap (r2b_wrap),
|
| 529 |
|
|
.r2b_raddr (r2b_raddr),
|
| 530 |
|
|
.r2b_caddr (r2b_caddr),
|
| 531 |
|
|
.r2b_len (r2b_len),
|
| 532 |
|
|
.r2b_write (r2b_write),
|
| 533 |
|
|
.b2r_ack (i2r_ack[3]),
|
| 534 |
|
|
.sdr_dma_last(rank_ba_last[3]),
|
| 535 |
|
|
|
| 536 |
|
|
/* Transfer request to xfr_ctl */
|
| 537 |
|
|
.b2x_req (i2x_req[3]),
|
| 538 |
|
|
.b2x_start (i2x_start[3]),
|
| 539 |
|
|
.b2x_last (i2x_last[3]),
|
| 540 |
|
|
.b2x_wrap (i2x_wrap[3]),
|
| 541 |
|
|
.b2x_id (i2x_id3),
|
| 542 |
|
|
.b2x_addr (i2x_addr3),
|
| 543 |
|
|
.b2x_len (i2x_len3),
|
| 544 |
|
|
.b2x_cmd (i2x_cmd3),
|
| 545 |
|
|
.x2b_ack (x2i_ack[3]),
|
| 546 |
|
|
|
| 547 |
|
|
/* Status to/from xfr_ctl */
|
| 548 |
|
|
.tras_ok (tras_ok[3]),
|
| 549 |
|
|
.xfr_ok (xfr_ok[3]),
|
| 550 |
|
|
.x2b_refresh (x2b_refresh),
|
| 551 |
|
|
.x2b_pre_ok (x2b_pre_ok[3]),
|
| 552 |
|
|
.x2b_act_ok (x2b_act_ok),
|
| 553 |
|
|
.x2b_rdok (x2b_rdok),
|
| 554 |
|
|
.x2b_wrok (x2b_wrok),
|
| 555 |
|
|
|
| 556 |
|
|
.bank_row(bank3_row),
|
| 557 |
|
|
|
| 558 |
|
|
/* SDRAM Timing */
|
| 559 |
|
|
.tras_delay (tras_delay),
|
| 560 |
|
|
.trp_delay (trp_delay),
|
| 561 |
|
|
.trcd_delay (trcd_delay));
|
| 562 |
|
|
|
| 563 |
|
|
|
| 564 |
|
|
/* address for current xfr, debug only */
|
| 565 |
|
|
wire [12:0] cur_row = (xfr_bank_sel==3) ? bank3_row:
|
| 566 |
|
|
(xfr_bank_sel==2) ? bank2_row:
|
| 567 |
|
|
(xfr_bank_sel==1) ? bank1_row: bank0_row;
|
| 568 |
|
|
|
| 569 |
|
|
|
| 570 |
|
|
|
| 571 |
|
|
endmodule // sdr_bank_ctl
|
