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dinesha |
//////////////////////////////////////////////////////////////////////
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//// ////
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//// SPI Clkgen Module ////
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//// ////
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//// This file is part of the YIFive cores project ////
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//// http://www.opencores.org/cores/yifive/ ////
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//// ////
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//// Description ////
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//// This is SPI Master Clock Generation control logic. ////
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//// This logic also generate spi clock rise and fall pulse ////
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//// Basis assumption is master clock is 2x time spi clock ////
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//// 1. spi fall pulse is used to transmit spi data ////
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//// 2. spi rise pulse is used to received spi data ////
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//// SPI Master Top module ////
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//// ////
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//// To Do: ////
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//// nothing ////
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//// ////
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//// Author(s): ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// ////
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//// Revision: ////
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//// 0.1 - 16th Feb 2021, Dinesh A ////
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//// Initial version ////
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//// 0.2 - 24th Mar 2021, Dinesh A ////
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//// 1. Comments are added ////
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//// 2. RTL clean-up done and the output are registred ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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module spim_clkgen
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(
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input logic clk,
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input logic rstn,
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input logic en,
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input logic [7:0] cfg_sck_period,
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output logic spi_clk,
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output logic spi_fall,
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output logic spi_rise
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);
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logic [7:0] sck_half_period;
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logic [7:0] clk_cnt;
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assign sck_half_period = {1'b0, cfg_sck_period[7:1]};
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// The first transition on the sck_toggle happens one SCK period
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// after en is asserted
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always @(posedge clk or negedge rstn) begin
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if(!rstn) begin
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clk_cnt <= 'h1;
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spi_clk <= 1'b1;
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spi_fall <= 1'b0;
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spi_rise <= 1'b0;
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end // if (!reset_n)
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else
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begin
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if(en)
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begin
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if(clk_cnt == sck_half_period)
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begin
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spi_clk <= 1'b0;
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end // if (clk_cnt == sck_half_period)
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else if(clk_cnt == cfg_sck_period) begin
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spi_clk <= 1'b1;
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end
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end else begin
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spi_clk <= 1'b1;
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end // else: !if(en)
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end // else: !if(!reset_n)
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end // always @ (posedge clk or negedge reset_n)
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// Generate Free runnng spi_fall and rise pulse
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// after en is asserted
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always @(posedge clk or negedge rstn) begin
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if(!rstn) begin
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clk_cnt <= 'h1;
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spi_fall <= 1'b0;
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spi_rise <= 1'b0;
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end // if (!reset_n)
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else
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begin
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if(clk_cnt == sck_half_period)
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begin
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spi_fall <= 1'b0;
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spi_rise <= 1'b1;
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clk_cnt <= clk_cnt + 1'b1;
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end // if (clk_cnt == sck_half_period)
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else begin
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if(clk_cnt == cfg_sck_period)
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begin
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spi_fall <= 1'b1;
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spi_rise <= 1'b0;
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clk_cnt <= 'h1;
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end // if (clk_cnt == cfg_sck_period)
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else
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begin
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clk_cnt <= clk_cnt + 1'b1;
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spi_fall <= 1'b0;
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spi_rise <= 1'b0;
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end // else: !if(clk_cnt == cfg_sck_period)
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end // else: !if(clk_cnt == sck_half_period)
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end // else: !if(!reset_n)
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end // always @ (posedge clk or negedge reset_n)
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dinesha |
endmodule
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