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dinesha |
/// Copyright by Syntacore LLC © 2016-2020. See LICENSE for details
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/// @file
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/// @brief Trigger Debug Unit (TDU)
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///
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//------------------------------------------------------------------------------
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//
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// Functionality:
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// - Provides read/write interface for TDU CSRs
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// - Provides triggers functionality:
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// - Supports triggers either in both Debug and M modes or in Debug mode only
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// - Supports virtual address matching (load, store, exec) triggers
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// - Supports instruction count triggers
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// - Supports the following actions on trigger firing:
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// - Breakpoint exception raising
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// - Debug Mode entering
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// - Supports triggers chaining
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//
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// Structure:
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// - CSR read/write i/f
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// - TDU CSRs:
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// - TSELECT
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// - TDATA1/MCONTROL/ICOUNT
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// - TDATA2
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// - TINFO
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// - TDU <-> EXU i/f
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// - TDU <-> LSU i/f
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// - TDU <-> HDU i/f
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//------------------------------------------------------------------------------
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`include "scr1_arch_description.svh"
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`ifdef SCR1_TDU_EN
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`include "scr1_riscv_isa_decoding.svh"
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`include "scr1_tdu.svh"
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module scr1_pipe_tdu (
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// Common signals
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input logic rst_n, // TDU reset
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input logic clk, // TDU clock
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input logic clk_en, // TDU clock enable
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input logic tdu_dsbl_i, // TDU Disable
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// TDU <-> CSR interface
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input logic csr2tdu_req_i, // CSR-TDU i/f request
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input type_scr1_csr_cmd_sel_e csr2tdu_cmd_i, // CSR-TDU i/f command
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input logic [SCR1_CSR_ADDR_TDU_OFFS_W-1:0] csr2tdu_addr_i, // CSR-TDU i/f address
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input logic [SCR1_TDU_DATA_W-1:0] csr2tdu_wdata_i, // CSR-TDU i/f write data
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output logic [SCR1_TDU_DATA_W-1:0] tdu2csr_rdata_o, // CSR-TDU i/f read data
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output type_scr1_csr_resp_e tdu2csr_resp_o, // CSR-TDU i/f response
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// TDU <-> EXU interface
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input type_scr1_brkm_instr_mon_s exu2tdu_imon_i, // Instruction stream monitoring
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output logic [SCR1_TDU_ALLTRIG_NUM-1 : 0] tdu2exu_ibrkpt_match_o, // Instruction BP match
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output logic tdu2exu_ibrkpt_exc_req_o, // Instruction BP exception request
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input logic [SCR1_TDU_ALLTRIG_NUM-1 : 0] exu2tdu_bp_retire_i, // Map of BPs being retired
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// TDU <-> LSU interface
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`ifndef SCR1_TDU_EN
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output logic tdu2lsu_brk_en_o, // TDU-LSU Breakpoint enable
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`endif // SCR1_TDU_EN
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output logic tdu2lsu_ibrkpt_exc_req_o, // TDU-LSU Instruction BP exception request
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input type_scr1_brkm_lsu_mon_s lsu2tdu_dmon_i, // TDU-LSU Data address stream monitoring
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output logic [SCR1_TDU_MTRIG_NUM-1 : 0] tdu2lsu_dbrkpt_match_o, // TDU-LSU Data BP match
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output logic tdu2lsu_dbrkpt_exc_req_o, // TDU-LSU Data BP exception request
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// TDU <-> HDU interface
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output logic tdu2hdu_dmode_req_o // Debug Mode redirection request
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);
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//------------------------------------------------------------------------------
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// Local parameters declaration
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//------------------------------------------------------------------------------
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localparam int unsigned MTRIG_NUM = SCR1_TDU_MTRIG_NUM;
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localparam int unsigned ALLTRIG_NUM = SCR1_TDU_ALLTRIG_NUM;
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localparam int unsigned ALLTRIG_W = $clog2(ALLTRIG_NUM+1);
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//------------------------------------------------------------------------------
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// Local signals declaration
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//------------------------------------------------------------------------------
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// TDU CSRs read/write i/f signals
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//------------------------------------------------------------------------------
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// Write signals
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logic csr_wr_req;
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logic [SCR1_TDU_DATA_W-1:0] csr_wr_data;
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// Register select
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logic csr_addr_tselect;
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logic [MTRIG_NUM-1:0] csr_addr_mcontrol;
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logic [MTRIG_NUM-1:0] csr_addr_tdata2;
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`ifdef SCR1_TDU_ICOUNT_EN
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logic csr_addr_icount;
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`endif // SCR1_TDU_ICOUNT_EN
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// TDU CSRs
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//------------------------------------------------------------------------------
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// TSELECT register
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logic csr_tselect_upd;
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logic [ALLTRIG_W-1:0] csr_tselect_ff;
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// MCONTROL register
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logic [MTRIG_NUM-1:0] csr_mcontrol_wr_req;
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logic [MTRIG_NUM-1:0] csr_mcontrol_clk_en;
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logic [MTRIG_NUM-1:0] csr_mcontrol_upd;
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logic [MTRIG_NUM-1:0] csr_mcontrol_dmode_ff;
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logic [MTRIG_NUM-1:0] csr_mcontrol_dmode_next;
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logic [MTRIG_NUM-1:0] csr_mcontrol_m_ff;
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logic [MTRIG_NUM-1:0] csr_mcontrol_m_next;
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logic [MTRIG_NUM-1:0] csr_mcontrol_exec_ff;
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logic [MTRIG_NUM-1:0] csr_mcontrol_exec_next;
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logic [MTRIG_NUM-1:0] csr_mcontrol_load_ff;
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logic [MTRIG_NUM-1:0] csr_mcontrol_load_next;
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logic [MTRIG_NUM-1:0] csr_mcontrol_store_ff;
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logic [MTRIG_NUM-1:0] csr_mcontrol_store_next;
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logic [MTRIG_NUM-1:0] csr_mcontrol_action_ff;
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logic [MTRIG_NUM-1:0] csr_mcontrol_action_next;
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logic [MTRIG_NUM-1:0] csr_mcontrol_hit_ff;
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logic [MTRIG_NUM-1:0] csr_mcontrol_hit_next;
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logic [MTRIG_NUM-1:0] csr_mcontrol_exec_hit;
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logic [MTRIG_NUM-1:0] csr_mcontrol_ldst_hit;
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// ICOUNT register
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`ifdef SCR1_TDU_ICOUNT_EN
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logic csr_icount_wr_req;
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logic csr_icount_clk_en;
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logic csr_icount_upd;
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logic csr_icount_dmode_ff;
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logic csr_icount_dmode_next;
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logic csr_icount_m_ff;
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logic csr_icount_m_next;
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logic csr_icount_action_ff;
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logic csr_icount_action_next;
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logic csr_icount_hit_ff;
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logic csr_icount_hit_next;
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logic [SCR1_TDU_ICOUNT_COUNT_HI-SCR1_TDU_ICOUNT_COUNT_LO:0]
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csr_icount_count_ff;
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logic [SCR1_TDU_ICOUNT_COUNT_HI-SCR1_TDU_ICOUNT_COUNT_LO:0]
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csr_icount_count_next;
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logic csr_icount_skip_ff;
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logic csr_icount_skip_next;
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logic csr_icount_decr_en;
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logic csr_icount_count_decr;
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logic csr_icount_skip_dsbl;
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logic csr_icount_hit;
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`endif // SCR1_TDU_ICOUNT_EN
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// TDATA2 register
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logic [MTRIG_NUM-1:0] csr_tdata2_upd;
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logic [MTRIG_NUM-1:0] csr_tdata2_ff [SCR1_TDU_DATA_W-1:0];
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//------------------------------------------------------------------------------
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// CSR read/write interface
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//------------------------------------------------------------------------------
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// Read logic
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//------------------------------------------------------------------------------
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assign tdu2csr_resp_o = csr2tdu_req_i ? SCR1_CSR_RESP_OK : SCR1_CSR_RESP_ER;
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integer i;
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always_comb begin
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i = 0; // yosys latch warning fix
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tdu2csr_rdata_o = '0;
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if (csr2tdu_req_i) begin
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case (csr2tdu_addr_i)
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SCR1_CSR_ADDR_TDU_OFFS_TSELECT: begin
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tdu2csr_rdata_o = {'0, csr_tselect_ff};
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end
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SCR1_CSR_ADDR_TDU_OFFS_TDATA2 : begin
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for(i = 0; i < MTRIG_NUM; i=i+1) begin // cp.4
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if(csr_tselect_ff == ALLTRIG_W'(i)) begin
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tdu2csr_rdata_o = csr_tdata2_ff[i];
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end
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end
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end
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SCR1_CSR_ADDR_TDU_OFFS_TDATA1 : begin
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for(i = 0; i < MTRIG_NUM; i=i+1) begin // cp.4
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if(csr_tselect_ff == ALLTRIG_W'(i)) begin
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tdu2csr_rdata_o[SCR1_TDU_TDATA1_TYPE_HI:
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SCR1_TDU_TDATA1_TYPE_LO] = SCR1_TDU_MCONTROL_TYPE_VAL;
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tdu2csr_rdata_o[SCR1_TDU_TDATA1_DMODE] = csr_mcontrol_dmode_ff[i];
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tdu2csr_rdata_o[SCR1_TDU_MCONTROL_MASKMAX_HI:
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SCR1_TDU_MCONTROL_MASKMAX_LO] = SCR1_TDU_MCONTROL_MASKMAX_VAL;
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tdu2csr_rdata_o[SCR1_TDU_MCONTROL_HIT] = csr_mcontrol_hit_ff[i];
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tdu2csr_rdata_o[SCR1_TDU_MCONTROL_SELECT] = SCR1_TDU_MCONTROL_SELECT_VAL;
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tdu2csr_rdata_o[SCR1_TDU_MCONTROL_TIMING] = SCR1_TDU_MCONTROL_TIMING_VAL;
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tdu2csr_rdata_o[SCR1_TDU_MCONTROL_ACTION_HI:
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SCR1_TDU_MCONTROL_ACTION_LO] = {5'b0, csr_mcontrol_action_ff[i]};
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tdu2csr_rdata_o[SCR1_TDU_MCONTROL_CHAIN] = 1'b0;
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tdu2csr_rdata_o[SCR1_TDU_MCONTROL_MATCH_HI:
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SCR1_TDU_MCONTROL_MATCH_LO] = 4'b0;
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tdu2csr_rdata_o[SCR1_TDU_MCONTROL_M] = csr_mcontrol_m_ff[i];
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tdu2csr_rdata_o[SCR1_TDU_MCONTROL_RESERVEDA] = SCR1_TDU_MCONTROL_RESERVEDA_VAL;
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tdu2csr_rdata_o[SCR1_TDU_MCONTROL_S] = 1'b0;
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tdu2csr_rdata_o[SCR1_TDU_MCONTROL_U] = 1'b0;
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tdu2csr_rdata_o[SCR1_TDU_MCONTROL_EXECUTE] = csr_mcontrol_exec_ff [i];
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tdu2csr_rdata_o[SCR1_TDU_MCONTROL_STORE] = csr_mcontrol_store_ff[i];
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tdu2csr_rdata_o[SCR1_TDU_MCONTROL_LOAD] = csr_mcontrol_load_ff [i];
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end
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end
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`ifdef SCR1_TDU_ICOUNT_EN
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if(csr_tselect_ff == ALLTRIG_W'(SCR1_TDU_ALLTRIG_NUM - 1'b1)) begin
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tdu2csr_rdata_o[SCR1_TDU_TDATA1_TYPE_HI:
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SCR1_TDU_TDATA1_TYPE_LO] = SCR1_TDU_ICOUNT_TYPE_VAL;
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tdu2csr_rdata_o[SCR1_TDU_TDATA1_DMODE] = csr_icount_dmode_ff;
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tdu2csr_rdata_o[SCR1_TDU_ICOUNT_HIT] = csr_icount_hit_ff;
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tdu2csr_rdata_o[SCR1_TDU_ICOUNT_COUNT_HI:
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SCR1_TDU_ICOUNT_COUNT_LO] = csr_icount_count_ff;
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tdu2csr_rdata_o[SCR1_TDU_ICOUNT_U] = 1'b0;
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tdu2csr_rdata_o[SCR1_TDU_ICOUNT_S] = 1'b0;
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tdu2csr_rdata_o[SCR1_TDU_ICOUNT_M] = csr_icount_m_ff;
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tdu2csr_rdata_o[SCR1_TDU_ICOUNT_ACTION_HI:
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SCR1_TDU_ICOUNT_ACTION_LO] = {5'b0, csr_icount_action_ff};
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end
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`endif // SCR1_TDU_ICOUNT_EN
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end
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SCR1_CSR_ADDR_TDU_OFFS_TINFO : begin
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for(i = 0; i < MTRIG_NUM; i=i+1) begin // cp.4
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if(csr_tselect_ff == ALLTRIG_W'(i)) begin
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tdu2csr_rdata_o[SCR1_TDU_MCONTROL_TYPE_VAL] = 1'b1;
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end
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end
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`ifdef SCR1_TDU_ICOUNT_EN
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if(csr_tselect_ff == ALLTRIG_W'(SCR1_TDU_ALLTRIG_NUM - 1'b1)) begin
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tdu2csr_rdata_o[SCR1_TDU_ICOUNT_TYPE_VAL] = 1'b1;
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end
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`endif // SCR1_TDU_ICOUNT_EN
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end
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default : begin
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end
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endcase
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end
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end
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// Write logic
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//------------------------------------------------------------------------------
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always_comb begin
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csr_wr_req = 1'b0;
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csr_wr_data = '0;
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case (csr2tdu_cmd_i)
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SCR1_CSR_CMD_WRITE: begin
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csr_wr_req = 1'b1;
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csr_wr_data = csr2tdu_wdata_i;
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end
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SCR1_CSR_CMD_SET : begin
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csr_wr_req = |csr2tdu_wdata_i;
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csr_wr_data = tdu2csr_rdata_o | csr2tdu_wdata_i;
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end
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SCR1_CSR_CMD_CLEAR: begin
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csr_wr_req = |csr2tdu_wdata_i;
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csr_wr_data = tdu2csr_rdata_o & ~csr2tdu_wdata_i;
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end
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default : begin
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end
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endcase
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end
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// Register selection
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//------------------------------------------------------------------------------
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integer k;
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always_comb begin
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k = 0; // yosys latch warning fix
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csr_addr_tselect = 1'b0;
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csr_addr_tdata2 = '0;
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csr_addr_mcontrol = '0;
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`ifdef SCR1_TDU_ICOUNT_EN
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csr_addr_icount = '0;
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`endif // SCR1_TDU_ICOUNT_EN
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if (csr2tdu_req_i) begin
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case (csr2tdu_addr_i)
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SCR1_CSR_ADDR_TDU_OFFS_TSELECT: begin
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csr_addr_tselect = 1'b1;
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end
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SCR1_CSR_ADDR_TDU_OFFS_TDATA1 : begin
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for(k = 0; k < MTRIG_NUM; k=k+1) begin
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if(csr_tselect_ff == ALLTRIG_W'(k)) begin
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|
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csr_addr_mcontrol[k] = 1'b1;
|
288 |
|
|
end
|
289 |
|
|
end
|
290 |
|
|
`ifdef SCR1_TDU_ICOUNT_EN
|
291 |
|
|
if(csr_tselect_ff == ALLTRIG_W'(SCR1_TDU_ALLTRIG_NUM - 1'b1)) begin
|
292 |
|
|
csr_addr_icount = 1'b1;
|
293 |
|
|
end
|
294 |
|
|
`endif // SCR1_TDU_ICOUNT_EN
|
295 |
|
|
end
|
296 |
|
|
SCR1_CSR_ADDR_TDU_OFFS_TDATA2 : begin
|
297 |
|
|
for(k = 0; k < MTRIG_NUM; k=k+1) begin // cp.4
|
298 |
|
|
if(csr_tselect_ff == ALLTRIG_W'(k) ) begin
|
299 |
|
|
csr_addr_tdata2[k] = 1'b1;
|
300 |
|
|
end
|
301 |
|
|
end
|
302 |
|
|
end
|
303 |
|
|
default : begin
|
304 |
|
|
end
|
305 |
|
|
endcase
|
306 |
|
|
end
|
307 |
|
|
end
|
308 |
|
|
|
309 |
|
|
//------------------------------------------------------------------------------
|
310 |
|
|
// TDU CSRs
|
311 |
|
|
//------------------------------------------------------------------------------
|
312 |
|
|
//
|
313 |
|
|
// TDU CSRs consist of the following registers:
|
314 |
|
|
// - TSELECT
|
315 |
|
|
// - TDATA1/MCONTROL/ICOUNT (depending on the type field value)
|
316 |
|
|
// - TDATA2
|
317 |
|
|
//
|
318 |
|
|
|
319 |
|
|
// TSELECT register
|
320 |
|
|
//------------------------------------------------------------------------------
|
321 |
|
|
// Determines which trigger is accessible through the other trigger registers
|
322 |
|
|
|
323 |
|
|
assign csr_tselect_upd = clk_en & csr_addr_tselect & csr_wr_req
|
324 |
|
|
& (csr_wr_data[ALLTRIG_W-1:0] < ALLTRIG_W'(ALLTRIG_NUM));
|
325 |
|
|
|
326 |
|
|
always_ff @(negedge rst_n, posedge clk) begin
|
327 |
|
|
if(~rst_n) begin
|
328 |
|
|
csr_tselect_ff <= '0;
|
329 |
|
|
end else if(csr_tselect_upd) begin
|
330 |
|
|
csr_tselect_ff <= csr_wr_data[ALLTRIG_W-1:0];
|
331 |
|
|
end
|
332 |
|
|
end
|
333 |
|
|
|
334 |
|
|
`ifdef SCR1_TDU_ICOUNT_EN
|
335 |
|
|
// ICOUNT register
|
336 |
|
|
//------------------------------------------------------------------------------
|
337 |
|
|
// Provides a trigger that fires when the certain number of instructions has retired
|
338 |
|
|
// Is intended to be used as a single step trigger (in this case count must be 1)
|
339 |
|
|
|
340 |
|
|
assign csr_icount_wr_req = csr_addr_icount & csr_wr_req;
|
341 |
|
|
assign csr_icount_clk_en = clk_en & (csr_icount_wr_req | csr_icount_m_ff);
|
342 |
|
|
assign csr_icount_upd = ~csr_icount_dmode_ff
|
343 |
|
|
? csr_icount_wr_req
|
344 |
|
|
: tdu_dsbl_i & csr_icount_wr_req;
|
345 |
|
|
|
346 |
|
|
always_ff @(negedge rst_n, posedge clk) begin
|
347 |
|
|
if(~rst_n) begin
|
348 |
|
|
csr_icount_dmode_ff <= 1'b0;
|
349 |
|
|
csr_icount_m_ff <= 1'b0;
|
350 |
|
|
csr_icount_action_ff <= 1'b0;
|
351 |
|
|
csr_icount_hit_ff <= 1'b0;
|
352 |
|
|
csr_icount_count_ff <= '0;
|
353 |
|
|
csr_icount_skip_ff <= 1'b0;
|
354 |
|
|
end else if (csr_icount_clk_en) begin
|
355 |
|
|
csr_icount_dmode_ff <= csr_icount_dmode_next;
|
356 |
|
|
csr_icount_m_ff <= csr_icount_m_next;
|
357 |
|
|
csr_icount_action_ff <= csr_icount_action_next;
|
358 |
|
|
csr_icount_hit_ff <= csr_icount_hit_next;
|
359 |
|
|
csr_icount_count_ff <= csr_icount_count_next;
|
360 |
|
|
csr_icount_skip_ff <= csr_icount_skip_next;
|
361 |
|
|
end
|
362 |
|
|
end
|
363 |
|
|
|
364 |
|
|
assign csr_icount_decr_en = (~tdu_dsbl_i & csr_icount_m_ff)
|
365 |
|
|
? exu2tdu_imon_i.vd & (csr_icount_count_ff != 14'b0)
|
366 |
|
|
: 1'b0;
|
367 |
|
|
assign csr_icount_count_decr = exu2tdu_imon_i.req & csr_icount_decr_en & ~csr_icount_skip_ff;
|
368 |
|
|
assign csr_icount_skip_dsbl = exu2tdu_imon_i.req & csr_icount_decr_en & csr_icount_skip_ff;
|
369 |
|
|
|
370 |
|
|
always_comb begin
|
371 |
|
|
if (csr_icount_upd) begin
|
372 |
|
|
csr_icount_dmode_next = csr_wr_data[SCR1_TDU_TDATA1_DMODE];
|
373 |
|
|
csr_icount_m_next = csr_wr_data[SCR1_TDU_ICOUNT_M];
|
374 |
|
|
csr_icount_action_next = (csr_wr_data[SCR1_TDU_ICOUNT_ACTION_HI
|
375 |
|
|
:SCR1_TDU_ICOUNT_ACTION_LO] == 'b1);
|
376 |
|
|
csr_icount_hit_next = csr_wr_data[SCR1_TDU_ICOUNT_HIT];
|
377 |
|
|
csr_icount_count_next = csr_wr_data[SCR1_TDU_ICOUNT_COUNT_HI:SCR1_TDU_ICOUNT_COUNT_LO];
|
378 |
|
|
end else begin
|
379 |
|
|
csr_icount_dmode_next = csr_icount_dmode_ff;
|
380 |
|
|
csr_icount_m_next = csr_icount_m_ff;
|
381 |
|
|
csr_icount_action_next = csr_icount_action_ff;
|
382 |
|
|
csr_icount_hit_next = exu2tdu_bp_retire_i[ALLTRIG_NUM - 1'b1]
|
383 |
|
|
? 1'b1
|
384 |
|
|
: csr_icount_hit_ff;
|
385 |
|
|
csr_icount_count_next = csr_icount_count_decr
|
386 |
|
|
? csr_icount_count_ff - 1'b1
|
387 |
|
|
: csr_icount_count_ff;
|
388 |
|
|
end
|
389 |
|
|
end
|
390 |
|
|
|
391 |
|
|
assign csr_icount_skip_next = csr_icount_wr_req ? csr_wr_data[SCR1_TDU_ICOUNT_M]
|
392 |
|
|
: csr_icount_skip_dsbl ? 1'b0
|
393 |
|
|
: csr_icount_skip_ff;
|
394 |
|
|
`endif // SCR1_TDU_ICOUNT_EN
|
395 |
|
|
|
396 |
|
|
// MCONTROL registers
|
397 |
|
|
//------------------------------------------------------------------------------
|
398 |
|
|
// Provides a trigger that fires on the virtual address (stored in TDATA2) match
|
399 |
|
|
// (load, store, exec options supported). Triggers chaining supported
|
400 |
|
|
|
401 |
|
|
genvar trig;
|
402 |
|
|
generate
|
403 |
|
|
for (trig = 0; $unsigned(trig) < MTRIG_NUM; trig=trig+1) begin : gblock_mtrig
|
404 |
|
|
|
405 |
|
|
assign csr_mcontrol_wr_req[trig] = csr_addr_mcontrol[trig] & csr_wr_req;
|
406 |
|
|
assign csr_mcontrol_clk_en[trig] = clk_en
|
407 |
|
|
& (csr_mcontrol_wr_req[trig] | csr_mcontrol_m_ff[trig]);
|
408 |
|
|
assign csr_mcontrol_upd [trig] = ~csr_mcontrol_dmode_ff[trig]
|
409 |
|
|
? csr_mcontrol_wr_req[trig]
|
410 |
|
|
: tdu_dsbl_i & csr_mcontrol_wr_req[trig];
|
411 |
|
|
|
412 |
|
|
always_ff @(negedge rst_n, posedge clk) begin
|
413 |
|
|
if(~rst_n) begin
|
414 |
|
|
csr_mcontrol_dmode_ff [trig] <= 1'b0;
|
415 |
|
|
csr_mcontrol_m_ff [trig] <= 1'b0;
|
416 |
|
|
csr_mcontrol_exec_ff [trig] <= 1'b0;
|
417 |
|
|
csr_mcontrol_load_ff [trig] <= 1'b0;
|
418 |
|
|
csr_mcontrol_store_ff [trig] <= 1'b0;
|
419 |
|
|
csr_mcontrol_action_ff[trig] <= 1'b0;
|
420 |
|
|
csr_mcontrol_hit_ff [trig] <= 1'b0;
|
421 |
|
|
end else if(csr_mcontrol_clk_en[trig]) begin
|
422 |
|
|
csr_mcontrol_dmode_ff [trig] <= csr_mcontrol_dmode_next[trig];
|
423 |
|
|
csr_mcontrol_m_ff [trig] <= csr_mcontrol_m_next[trig];
|
424 |
|
|
csr_mcontrol_exec_ff [trig] <= csr_mcontrol_exec_next[trig];
|
425 |
|
|
csr_mcontrol_load_ff [trig] <= csr_mcontrol_load_next[trig];
|
426 |
|
|
csr_mcontrol_store_ff [trig] <= csr_mcontrol_store_next[trig];
|
427 |
|
|
csr_mcontrol_action_ff[trig] <= csr_mcontrol_action_next[trig];
|
428 |
|
|
csr_mcontrol_hit_ff [trig] <= csr_mcontrol_hit_next[trig];
|
429 |
|
|
end
|
430 |
|
|
end
|
431 |
|
|
|
432 |
|
|
always_comb begin
|
433 |
|
|
if (csr_mcontrol_upd[trig]) begin
|
434 |
|
|
csr_mcontrol_dmode_next [trig] = csr_wr_data[SCR1_TDU_TDATA1_DMODE];
|
435 |
|
|
csr_mcontrol_m_next [trig] = csr_wr_data[SCR1_TDU_MCONTROL_M];
|
436 |
|
|
csr_mcontrol_exec_next [trig] = csr_wr_data[SCR1_TDU_MCONTROL_EXECUTE];
|
437 |
|
|
csr_mcontrol_load_next [trig] = csr_wr_data[SCR1_TDU_MCONTROL_LOAD];
|
438 |
|
|
csr_mcontrol_store_next [trig] = csr_wr_data[SCR1_TDU_MCONTROL_STORE];
|
439 |
|
|
csr_mcontrol_action_next[trig] = (csr_wr_data[SCR1_TDU_MCONTROL_ACTION_HI
|
440 |
|
|
:SCR1_TDU_MCONTROL_ACTION_LO] == 'b1);
|
441 |
|
|
csr_mcontrol_hit_next [trig] = csr_wr_data[SCR1_TDU_MCONTROL_HIT];
|
442 |
|
|
end else begin
|
443 |
|
|
csr_mcontrol_dmode_next [trig] = csr_mcontrol_dmode_ff [trig];
|
444 |
|
|
csr_mcontrol_m_next [trig] = csr_mcontrol_m_ff [trig];
|
445 |
|
|
csr_mcontrol_exec_next [trig] = csr_mcontrol_exec_ff [trig];
|
446 |
|
|
csr_mcontrol_load_next [trig] = csr_mcontrol_load_ff [trig];
|
447 |
|
|
csr_mcontrol_store_next [trig] = csr_mcontrol_store_ff [trig];
|
448 |
|
|
csr_mcontrol_action_next[trig] = csr_mcontrol_action_ff[trig];
|
449 |
|
|
csr_mcontrol_hit_next [trig] = exu2tdu_bp_retire_i[trig]
|
450 |
|
|
? 1'b1
|
451 |
|
|
: csr_mcontrol_hit_ff[trig];
|
452 |
|
|
end
|
453 |
|
|
end
|
454 |
|
|
|
455 |
|
|
// TDATA2 register
|
456 |
|
|
//------------------------------------------------------------------------------
|
457 |
|
|
|
458 |
|
|
assign csr_tdata2_upd[trig] = ~csr_mcontrol_dmode_ff[trig]
|
459 |
|
|
? clk_en & csr_addr_tdata2[trig] & csr_wr_req
|
460 |
|
|
: clk_en & csr_addr_tdata2[trig] & csr_wr_req & tdu_dsbl_i;
|
461 |
|
|
|
462 |
|
|
always_ff @(posedge clk) begin
|
463 |
|
|
if (csr_tdata2_upd[trig]) begin
|
464 |
|
|
csr_tdata2_ff[trig] <= csr_wr_data;
|
465 |
|
|
end
|
466 |
|
|
end
|
467 |
|
|
|
468 |
|
|
end
|
469 |
|
|
endgenerate // gblock_mtrig
|
470 |
|
|
|
471 |
|
|
//------------------------------------------------------------------------------
|
472 |
|
|
// TDU <-> EXU interface
|
473 |
|
|
//------------------------------------------------------------------------------
|
474 |
|
|
|
475 |
|
|
assign csr_icount_hit = ~tdu_dsbl_i & csr_icount_m_ff
|
476 |
|
|
? exu2tdu_imon_i.vd & (csr_icount_count_ff == 14'b1) & ~csr_icount_skip_ff
|
477 |
|
|
: 1'b0;
|
478 |
|
|
|
479 |
|
|
`ifndef SCR1_TDU_ICOUNT_EN
|
480 |
|
|
assign tdu2exu_ibrkpt_match_o = csr_mcontrol_exec_hit;
|
481 |
|
|
assign tdu2exu_ibrkpt_exc_req_o = |csr_mcontrol_exec_hit;
|
482 |
|
|
`else
|
483 |
|
|
assign tdu2exu_ibrkpt_match_o = {csr_icount_hit, csr_mcontrol_exec_hit};
|
484 |
|
|
assign tdu2exu_ibrkpt_exc_req_o = |csr_mcontrol_exec_hit | csr_icount_hit;
|
485 |
|
|
`endif // SCR1_TDU_ICOUNT_EN
|
486 |
|
|
|
487 |
|
|
//------------------------------------------------------------------------------
|
488 |
|
|
// TDU <-> LSU interface
|
489 |
|
|
//------------------------------------------------------------------------------
|
490 |
|
|
|
491 |
|
|
// Breakpoint logic
|
492 |
|
|
//------------------------------------------------------------------------------
|
493 |
|
|
|
494 |
|
|
generate
|
495 |
|
|
for (trig = 0; $unsigned(trig) < MTRIG_NUM; trig=trig+1) begin : gblock_break_trig
|
496 |
|
|
assign csr_mcontrol_exec_hit[trig] = ~tdu_dsbl_i
|
497 |
|
|
& csr_mcontrol_m_ff[trig]
|
498 |
|
|
& csr_mcontrol_exec_ff[trig]
|
499 |
|
|
& exu2tdu_imon_i.vd
|
500 |
|
|
& exu2tdu_imon_i.addr == csr_tdata2_ff[trig];
|
501 |
|
|
end
|
502 |
|
|
endgenerate
|
503 |
|
|
|
504 |
|
|
`ifndef SCR1_TDU_ICOUNT_EN
|
505 |
|
|
assign tdu2lsu_ibrkpt_exc_req_o = |csr_mcontrol_exec_hit;
|
506 |
|
|
`else
|
507 |
|
|
assign tdu2lsu_ibrkpt_exc_req_o = |csr_mcontrol_exec_hit | csr_icount_hit;
|
508 |
|
|
`endif // SCR1_TDU_ICOUNT_EN
|
509 |
|
|
|
510 |
|
|
// Watchpoint logic
|
511 |
|
|
//------------------------------------------------------------------------------
|
512 |
|
|
|
513 |
|
|
generate
|
514 |
|
|
for( trig = 0; $unsigned(trig) < MTRIG_NUM; trig=trig+1 ) begin : gblock_watch_trig
|
515 |
|
|
assign csr_mcontrol_ldst_hit[trig] = ~tdu_dsbl_i
|
516 |
|
|
& csr_mcontrol_m_ff[trig]
|
517 |
|
|
& lsu2tdu_dmon_i.vd
|
518 |
|
|
& ( (csr_mcontrol_load_ff [trig] & lsu2tdu_dmon_i.load)
|
519 |
|
|
| (csr_mcontrol_store_ff[trig] & lsu2tdu_dmon_i.store))
|
520 |
|
|
& lsu2tdu_dmon_i.addr == csr_tdata2_ff[trig];
|
521 |
|
|
end
|
522 |
|
|
endgenerate
|
523 |
|
|
|
524 |
|
|
assign tdu2lsu_dbrkpt_match_o = csr_mcontrol_ldst_hit;
|
525 |
|
|
assign tdu2lsu_dbrkpt_exc_req_o = |csr_mcontrol_ldst_hit;
|
526 |
|
|
|
527 |
|
|
`ifndef SCR1_TDU_EN
|
528 |
|
|
assign tdu2lsu_brk_en_o = |csr_mcontrol_m_ff | csr_icount_m_ff;
|
529 |
|
|
`endif // SCR1_TDU_EN
|
530 |
|
|
|
531 |
|
|
//------------------------------------------------------------------------------
|
532 |
|
|
// TDU <-> HDU interface
|
533 |
|
|
//------------------------------------------------------------------------------
|
534 |
|
|
integer j;
|
535 |
|
|
always_comb begin
|
536 |
|
|
tdu2hdu_dmode_req_o = 1'b0;
|
537 |
|
|
|
538 |
|
|
for(j = 0; j < MTRIG_NUM; j=j+1) begin
|
539 |
|
|
tdu2hdu_dmode_req_o |= (csr_mcontrol_action_ff[j] & exu2tdu_bp_retire_i[j]);
|
540 |
|
|
end
|
541 |
|
|
`ifdef SCR1_TDU_ICOUNT_EN
|
542 |
|
|
tdu2hdu_dmode_req_o |= (csr_icount_action_ff & exu2tdu_bp_retire_i[ALLTRIG_NUM-1]);
|
543 |
|
|
`endif // SCR1_TDU_ICOUNT_EN
|
544 |
|
|
end
|
545 |
|
|
|
546 |
|
|
`ifdef SCR1_TRGT_SIMULATION
|
547 |
|
|
//------------------------------------------------------------------------------
|
548 |
|
|
// Assertion
|
549 |
|
|
//------------------------------------------------------------------------------
|
550 |
|
|
|
551 |
|
|
SVA_TDU_X_CONTROL : assert property (
|
552 |
|
|
@(negedge clk) disable iff (~rst_n)
|
553 |
|
|
!$isunknown({clk_en, tdu_dsbl_i, csr2tdu_req_i,
|
554 |
|
|
exu2tdu_imon_i.vd, lsu2tdu_dmon_i.vd, exu2tdu_bp_retire_i})
|
555 |
|
|
) else $error("TDU Error: control signals is X - %0b", {clk_en,
|
556 |
|
|
tdu_dsbl_i, csr2tdu_req_i, exu2tdu_imon_i.vd, lsu2tdu_dmon_i.vd, exu2tdu_bp_retire_i});
|
557 |
|
|
|
558 |
|
|
SVA_DM_X_CLK_EN : assert property (
|
559 |
|
|
@(negedge clk) disable iff (~rst_n)
|
560 |
|
|
!$isunknown(clk_en)
|
561 |
|
|
) else $error("TDU Error: clk_en control signals is X");
|
562 |
|
|
|
563 |
|
|
SVA_DM_X_DSBL : assert property (
|
564 |
|
|
@(negedge clk) disable iff (~rst_n)
|
565 |
|
|
!$isunknown(tdu_dsbl_i)
|
566 |
|
|
) else $error("TDU Error: tdu_dsbl_i control signals is X");
|
567 |
|
|
|
568 |
|
|
SVA_DM_X_CSR2TDU_REQ : assert property (
|
569 |
|
|
@(negedge clk) disable iff (~rst_n)
|
570 |
|
|
!$isunknown(csr2tdu_req_i)
|
571 |
|
|
) else $error("TDU Error: csr2tdu_req_i control signals is X");
|
572 |
|
|
|
573 |
|
|
SVA_DM_X_I_MON_VD : assert property (
|
574 |
|
|
@(negedge clk) disable iff (~rst_n)
|
575 |
|
|
!$isunknown(exu2tdu_imon_i.vd)
|
576 |
|
|
) else $error("TDU Error: exu2tdu_imon_i.vd control signals is X");
|
577 |
|
|
|
578 |
|
|
SVA_DM_X_D_MON_VD : assert property (
|
579 |
|
|
@(negedge clk) disable iff (~rst_n)
|
580 |
|
|
!$isunknown(lsu2tdu_dmon_i.vd)
|
581 |
|
|
) else $error("TDU Error: lsu2tdu_dmon_i.vd control signals is X");
|
582 |
|
|
|
583 |
|
|
SVA_DM_X_BP_RETIRE : assert property (
|
584 |
|
|
@(negedge clk) disable iff (~rst_n)
|
585 |
|
|
!$isunknown(exu2tdu_bp_retire_i)
|
586 |
|
|
) else $error("TDU Error: exu2tdu_bp_retire_i control signals is X");
|
587 |
|
|
|
588 |
|
|
SVA_TDU_X_CSR : assert property (
|
589 |
|
|
@(negedge clk) disable iff (~rst_n)
|
590 |
|
|
csr2tdu_req_i |-> !$isunknown({csr2tdu_cmd_i,csr2tdu_addr_i})
|
591 |
|
|
) else $error("TDU Error: csr is X");
|
592 |
|
|
|
593 |
|
|
SVA_TDU_XW_CSR : assert property (
|
594 |
|
|
@(negedge clk) disable iff (~rst_n)
|
595 |
|
|
(csr2tdu_req_i & csr_wr_req) |-> !$isunknown(csr2tdu_wdata_i)
|
596 |
|
|
) else $error("TDU Error: csr wdata is X ");
|
597 |
|
|
|
598 |
|
|
SVA_TDU_X_IMON : assert property (
|
599 |
|
|
@(negedge clk) disable iff (~rst_n)
|
600 |
|
|
exu2tdu_imon_i.vd |-> !$isunknown({exu2tdu_imon_i.req,exu2tdu_imon_i.addr})
|
601 |
|
|
) else $error("TDU Error: imonitor is X");
|
602 |
|
|
|
603 |
|
|
SVA_TDU_X_DMON : assert property (
|
604 |
|
|
@(negedge clk) disable iff (~rst_n)
|
605 |
|
|
lsu2tdu_dmon_i.vd |-> !$isunknown({lsu2tdu_dmon_i})
|
606 |
|
|
) else $error("TDU Error: dmonitor is X");
|
607 |
|
|
|
608 |
|
|
`endif // SCR1_TRGT_SIMULATION
|
609 |
|
|
|
610 |
|
|
endmodule : scr1_pipe_tdu
|
611 |
|
|
|
612 |
|
|
`endif // SCR1_TDU_EN
|