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[/] [yifive/] [trunk/] [caravel_yifive/] [verilog/] [rtl/] [syntacore/] [scr1/] [src/] [core.files] - Blame information for rev 12

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Line No. Rev Author Line
1 11 dinesha 
core/pipeline/scr1_pipe_hdu.sv
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core/pipeline/scr1_pipe_tdu.sv
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core/pipeline/scr1_ipic.sv
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core/pipeline/scr1_pipe_csr.sv
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core/pipeline/scr1_pipe_exu.sv
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core/pipeline/scr1_pipe_ialu.sv
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core/pipeline/scr1_pipe_idu.sv
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core/pipeline/scr1_pipe_ifu.sv
9 
core/pipeline/scr1_pipe_lsu.sv
10 
core/pipeline/scr1_pipe_mprf.sv
11 
core/pipeline/scr1_pipe_top.sv
12 
core/primitives/scr1_reset_cells.sv
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core/primitives/scr1_cg.sv
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core/scr1_clk_ctrl.sv
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core/scr1_tapc_shift_reg.sv
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core/scr1_tapc.sv
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core/scr1_tapc_synchronizer.sv
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core/scr1_core_top.sv
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core/scr1_dm.sv
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core/scr1_dmi.sv
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core/scr1_scu.sv

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