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[/] [yifive/] [trunk/] [caravel_yifive/] [verilog/] [rtl/] [syntacore/] [scr1/] [src/] [includes/] [scr1_hdu.svh] - Blame information for rev 12

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1 11 dinesha 
/// Copyright by Syntacore LLC © 2016-2021. See LICENSE for details
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/// @file
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/// @brief      HART Debug Unit definitions file
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///
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`ifndef SCR1_INCLUDE_HDU_DEFS
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`define SCR1_INCLUDE_HDU_DEFS
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`include "scr1_arch_description.svh"
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`include "scr1_csr.svh"
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`ifdef SCR1_MMU_EN
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 `define SCR1_HDU_FEATURE_MPRVEN
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`endif // SCR1_MMU_EN
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//==============================================================================
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// Parameters
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//==============================================================================
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//localparam int unsigned SCR1_HDU_DEBUGCSR_BASE_ADDR      = 12'h7B0;
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localparam int unsigned SCR1_HDU_DEBUGCSR_ADDR_SPAN      = 4; // YOSYS FIX
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localparam int unsigned SCR1_HDU_DEBUGCSR_ADDR_WIDTH     = $clog2(SCR1_HDU_DEBUGCSR_ADDR_SPAN);
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localparam bit [3:0]    SCR1_HDU_DEBUGCSR_DCSR_XDEBUGVER = 4'h4;
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localparam int unsigned SCR1_HDU_PBUF_ADDR_SPAN          = 8;
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localparam int unsigned SCR1_HDU_PBUF_ADDR_WIDTH         = $clog2(SCR1_HDU_PBUF_ADDR_SPAN);
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localparam int unsigned SCR1_HDU_DATA_REG_WIDTH          = 32;
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localparam int unsigned SCR1_HDU_CORE_INSTR_WIDTH        = 32;
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//==============================================================================
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// Types
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//==============================================================================
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// HART Debug States:
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typedef enum logic [1:0] {
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    SCR1_HDU_DBGSTATE_RESET         = 2'b00,
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    SCR1_HDU_DBGSTATE_RUN           = 2'b01,
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    SCR1_HDU_DBGSTATE_DHALTED       = 2'b10,
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    SCR1_HDU_DBGSTATE_DRUN          = 2'b11
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`ifdef SCR1_XPROP_EN
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    ,
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    SCR1_HDU_DBGSTATE_XXX           = 'X
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`endif // SCR1_XPROP_EN
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} type_scr1_hdu_dbgstates_e;
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typedef enum logic [1:0] {
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    SCR1_HDU_PBUFSTATE_IDLE          = 2'b00,
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    SCR1_HDU_PBUFSTATE_FETCH         = 2'b01,
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    SCR1_HDU_PBUFSTATE_EXCINJECT     = 2'b10,
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    SCR1_HDU_PBUFSTATE_WAIT4END      = 2'b11
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`ifdef SCR1_XPROP_EN
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    ,
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    SCR1_HDU_PBUFSTATE_XXX           = 'X
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`endif // SCR1_XPROP_EN
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} type_scr1_hdu_pbufstates_e;
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typedef enum logic {
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    SCR1_HDU_HARTCMD_RESUME         = 1'b0,
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    SCR1_HDU_HARTCMD_HALT           = 1'b1
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`ifdef SCR1_XPROP_EN
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    ,
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    SCR1_HDU_HARTCMD_XXX            = 1'bX
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`endif // SCR1_XPROP_EN
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} type_scr1_hdu_hart_command_e;
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typedef enum logic {
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    SCR1_HDU_FETCH_SRC_NORMAL       = 1'b0,
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    SCR1_HDU_FETCH_SRC_PBUF         = 1'b1
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`ifdef SCR1_XPROP_EN
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    ,
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    SCR1_HDU_FETCH_SRC_XXX          = 1'bX
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`endif // SCR1_XPROP_EN
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} type_scr1_hdu_fetch_src_e;
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typedef struct packed {
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    //logic                               reset_n;
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    logic                               except;
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    logic                               ebreak;
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    type_scr1_hdu_dbgstates_e           dbg_state;
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} type_scr1_hdu_hartstatus_s;
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// Debug Mode Redirection control:
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typedef struct packed {
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    logic                               sstep;          // Single Step
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    logic                               ebreak;         // Redirection after EBREAK execution
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} type_scr1_hdu_redirect_s;
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typedef struct packed {
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    logic                               irq_dsbl;
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    type_scr1_hdu_fetch_src_e           fetch_src;
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    logic                               pc_advmt_dsbl;
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    logic                               hwbrkpt_dsbl;
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    type_scr1_hdu_redirect_s            redirect;
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} type_scr1_hdu_runctrl_s;
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// HART Halt Status:
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typedef enum logic [2:0] {
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    SCR1_HDU_HALTCAUSE_NONE         = 3'b000,
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    SCR1_HDU_HALTCAUSE_EBREAK       = 3'b001,
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    SCR1_HDU_HALTCAUSE_TMREQ        = 3'b010,
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    SCR1_HDU_HALTCAUSE_DMREQ        = 3'b011,
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    SCR1_HDU_HALTCAUSE_SSTEP        = 3'b100,
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    SCR1_HDU_HALTCAUSE_RSTEXIT      = 3'b101
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`ifdef SCR1_XPROP_EN
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    ,
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    SCR1_HDU_HALTCAUSE_XXX          = 'X
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`endif // SCR1_XPROP_EN
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} type_scr1_hdu_haltcause_e;
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typedef struct packed {
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    logic                               except;
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    type_scr1_hdu_haltcause_e           cause;
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} type_scr1_hdu_haltstatus_s;
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// Debug CSR map
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localparam SCR1_HDU_DBGCSR_OFFS_DCSR       = SCR1_HDU_DEBUGCSR_ADDR_WIDTH'( 'd0 );
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localparam SCR1_HDU_DBGCSR_OFFS_DPC        = SCR1_HDU_DEBUGCSR_ADDR_WIDTH'( 'd1 );
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localparam SCR1_HDU_DBGCSR_OFFS_DSCRATCH0  = SCR1_HDU_DEBUGCSR_ADDR_WIDTH'( 'd2 );
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localparam SCR1_HDU_DBGCSR_OFFS_DSCRATCH1  = SCR1_HDU_DEBUGCSR_ADDR_WIDTH'( 'd3 );
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localparam bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_HDU_DBGCSR_ADDR_DCSR      = SCR1_CSR_ADDR_HDU_MBASE + SCR1_HDU_DBGCSR_OFFS_DCSR;
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localparam bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_HDU_DBGCSR_ADDR_DPC       = SCR1_CSR_ADDR_HDU_MBASE + SCR1_HDU_DBGCSR_OFFS_DPC;
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localparam bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_HDU_DBGCSR_ADDR_DSCRATCH0 = SCR1_CSR_ADDR_HDU_MBASE + SCR1_HDU_DBGCSR_OFFS_DSCRATCH0;
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localparam bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_HDU_DBGCSR_ADDR_DSCRATCH1 = SCR1_CSR_ADDR_HDU_MBASE + SCR1_HDU_DBGCSR_OFFS_DSCRATCH1;
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// Debug CSRs :: DCSR
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typedef enum int {
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    SCR1_HDU_DCSR_PRV_BIT_R         = 0,
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    SCR1_HDU_DCSR_PRV_BIT_L         = 1,
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    SCR1_HDU_DCSR_STEP_BIT          = 2,
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    SCR1_HDU_DCSR_RSRV0_BIT_R       = 3,
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    SCR1_HDU_DCSR_RSRV0_BIT_L       = 5,
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    SCR1_HDU_DCSR_CAUSE_BIT_R       = 6,
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    SCR1_HDU_DCSR_CAUSE_BIT_L       = 8,
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    SCR1_HDU_DCSR_RSRV1_BIT_R       = 9,
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    SCR1_HDU_DCSR_RSRV1_BIT_L       = 10,
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    SCR1_HDU_DCSR_STEPIE_BIT        = 11,
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    SCR1_HDU_DCSR_RSRV2_BIT_R       = 12,
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    SCR1_HDU_DCSR_RSRV2_BIT_L       = 14,
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    SCR1_HDU_DCSR_EBREAKM_BIT       = 15,
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    SCR1_HDU_DCSR_RSRV3_BIT_R       = 16,
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    SCR1_HDU_DCSR_RSRV3_BIT_L       = 27,
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    SCR1_HDU_DCSR_XDEBUGVER_BIT_R   = 28,
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    SCR1_HDU_DCSR_XDEBUGVER_BIT_L   = 31
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} type_scr1_hdu_dcsr_bits_e;
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//localparam int unsigned SCR1_HDU_DEBUGCSR_DCSR_PRV_WIDTH = SCR1_HDU_DCSR_PRV_BIT_L-SCR1_HDU_DCSR_PRV_BIT_R+1;
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typedef struct packed {
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    logic [SCR1_HDU_DCSR_XDEBUGVER_BIT_L-SCR1_HDU_DCSR_XDEBUGVER_BIT_R:0]   xdebugver;
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    logic [SCR1_HDU_DCSR_RSRV3_BIT_L-SCR1_HDU_DCSR_RSRV3_BIT_R:0]           rsrv3;
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    logic                                                                   ebreakm;
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    logic [SCR1_HDU_DCSR_RSRV2_BIT_L-SCR1_HDU_DCSR_RSRV2_BIT_R:0]           rsrv2;
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    logic                                                                   stepie;
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    logic [SCR1_HDU_DCSR_RSRV1_BIT_L-SCR1_HDU_DCSR_RSRV1_BIT_R:0]           rsrv1;
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    logic [SCR1_HDU_DCSR_CAUSE_BIT_L-SCR1_HDU_DCSR_CAUSE_BIT_R:0]           cause;
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    logic [SCR1_HDU_DCSR_RSRV0_BIT_L-SCR1_HDU_DCSR_RSRV0_BIT_R:0]           rsrv0;
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    logic                                                                   step;
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    logic [SCR1_HDU_DCSR_PRV_BIT_L-SCR1_HDU_DCSR_PRV_BIT_R:0]               prv;
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} type_scr1_hdu_dcsr_s;
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`endif // SCR1_INCLUDE_HDU_DEFS

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