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////  yifive Wishbone define for syntacore                        ////

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////  This file is part of the yifive cores project               ////

////  http://www.opencores.org/cores/yifive/                      ////

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////  Description:                                                ////

////     integrated wishbone i/f to Syntacore,scr1 core          ////

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////  To Do:                                                      ////

////    nothing                                                   ////

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////  Author(s):                                                  ////

////      - Dinesh Annayya, dinesha@opencores.org                 ////

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////  Revision :                                                  ////

////     v0:    June 7, 2021, Dinesh A                            ////

////             wishbone define added                            ////

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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////

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//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

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//     Orginal owner Details                                      ////

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/// Copyright by Syntacore LLC © 2016-2021. See LICENSE for details///

/// @file                                            ///

/// @brief      WB header file                                     ///

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`ifndef SCR1_WB_SVH

`define SCR1_WB_SVH

`include "scr1_arch_description.svh"

parameter SCR1_WB_WIDTH  = 32;

// Encoding for DATA SIZE

parameter logic [2:0] SCR1_DSIZE_8B    = 3'b000;

parameter logic [2:0] SCR1_DSIZE_16B   = 3'b001;

parameter logic [2:0] SCR1_DSIZE_32B   = 3'b010;

`endif // SCR1_WB_SVH