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dinesha |
/// Copyright by Syntacore LLC © 2016-2020. See LICENSE for details
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/// @file
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/// @brief Dual-port synchronous memory with byte enable inputs
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///
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`include "scr1_arch_description.svh"
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`ifdef SCR1_TCM_EN
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module scr1_dp_memory
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#(
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parameter SCR1_WIDTH = 32,
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parameter SCR1_SIZE = `SCR1_IMEM_AWIDTH'h00010000,
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parameter SCR1_NBYTES = SCR1_WIDTH / 8
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)
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(
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input logic clk,
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// Port A
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input logic rena,
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input logic [$clog2(SCR1_SIZE)-1:2] addra,
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output logic [SCR1_WIDTH-1:0] qa,
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// Port B
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input logic renb,
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input logic wenb,
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input logic [SCR1_NBYTES-1:0] webb,
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input logic [$clog2(SCR1_SIZE)-1:2] addrb,
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input logic [SCR1_WIDTH-1:0] datab,
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output logic [SCR1_WIDTH-1:0] qb
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);
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`ifdef SCR1_TRGT_FPGA_INTEL
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//-------------------------------------------------------------------------------
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// Local signal declaration
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//-------------------------------------------------------------------------------
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`ifdef SCR1_TRGT_FPGA_INTEL_MAX10
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(* ramstyle = "M9K" *) logic [SCR1_NBYTES-1:0][7:0] memory_array [0:(SCR1_SIZE/SCR1_NBYTES)-1];
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`elsif SCR1_TRGT_FPGA_INTEL_ARRIAV
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(* ramstyle = "M10K" *) logic [SCR1_NBYTES-1:0][7:0] memory_array [0:(SCR1_SIZE/SCR1_NBYTES)-1];
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`endif
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logic [3:0] wenbb;
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//-------------------------------------------------------------------------------
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// Port B memory behavioral description
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//-------------------------------------------------------------------------------
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assign wenbb = {4{wenb}} & webb;
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always_ff @(posedge clk) begin
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if (wenb) begin
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if (wenbb[0]) begin
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memory_array[addrb][0] <= datab[0+:8];
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end
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if (wenbb[1]) begin
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memory_array[addrb][1] <= datab[8+:8];
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end
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if (wenbb[2]) begin
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memory_array[addrb][2] <= datab[16+:8];
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end
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if (wenbb[3]) begin
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memory_array[addrb][3] <= datab[24+:8];
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end
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end
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qb <= memory_array[addrb];
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end
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//-------------------------------------------------------------------------------
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// Port A memory behavioral description
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//-------------------------------------------------------------------------------
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always_ff @(posedge clk) begin
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qa <= memory_array[addra];
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end
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`else // SCR1_TRGT_FPGA_INTEL
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// CASE: OTHERS - SCR1_TRGT_FPGA_XILINX, SIMULATION, ASIC etc
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localparam int unsigned RAM_SIZE_WORDS = SCR1_SIZE/SCR1_NBYTES;
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//-------------------------------------------------------------------------------
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// Local signal declaration
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//-------------------------------------------------------------------------------
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`ifdef SCR1_TRGT_FPGA_XILINX
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(* ram_style = "block" *) logic [SCR1_WIDTH-1:0] ram_block [RAM_SIZE_WORDS-1:0];
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`else // ASIC or SIMULATION
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logic [SCR1_WIDTH-1:0] ram_block [RAM_SIZE_WORDS-1:0];
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`endif
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//-------------------------------------------------------------------------------
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// Port A memory behavioral description
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//-------------------------------------------------------------------------------
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always_ff @(posedge clk) begin
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if (rena) begin
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qa <= ram_block[addra];
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end
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end
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//-------------------------------------------------------------------------------
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// Port B memory behavioral description
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//-------------------------------------------------------------------------------
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always_ff @(posedge clk) begin
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if (wenb) begin
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for (int i=0; i
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if (webb[i]) begin
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ram_block[addrb][i*8 +: 8] <= datab[i*8 +: 8];
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end
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end
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end
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if (renb) begin
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qb <= ram_block[addrb];
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end
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end
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`endif // SCR1_TRGT_FPGA_INTEL
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endmodule : scr1_dp_memory
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`endif // SCR1_TCM_EN
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