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[/] [yifive/] [trunk/] [caravel_yifive/] [verilog/] [rtl/] [syntacore/] [scr1/] [src/] [top/] [scr1_imem_router.sv] - Blame information for rev 21

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/// Copyright by Syntacore LLC © 2016-2021. See LICENSE for details
/// @file       
/// @brief      Instruction memory router
///
`include "scr1_memif.svh"
`include "scr1_arch_description.svh"
 
module scr1_imem_router
#(
    parameter SCR1_ADDR_MASK    = `SCR1_IMEM_AWIDTH'hFFFF0000,
    parameter SCR1_ADDR_PATTERN = `SCR1_IMEM_AWIDTH'h00010000
)
(
    // Control signals
    input   logic                           rst_n,
    input   logic                           clk,
 
    // Core interface
    output  logic                           imem_req_ack,
    input   logic                           imem_req,
    input   logic                           imem_cmd,
    input   logic [`SCR1_IMEM_AWIDTH-1:0]   imem_addr,
    output  logic [`SCR1_IMEM_DWIDTH-1:0]   imem_rdata,
    output  logic [1:0]                     imem_resp,
 
    // PORT0 interface
    input   logic                           port0_req_ack,
    output  logic                           port0_req,
    output  logic                           port0_cmd,
    output  logic [`SCR1_IMEM_AWIDTH-1:0]   port0_addr,
    input   logic [`SCR1_IMEM_DWIDTH-1:0]   port0_rdata,
    input   logic [1:0]                     port0_resp,
 
    // PORT1 interface
    input   logic                           port1_req_ack,
    output  logic                           port1_req,
    output  logic                           port1_cmd,
    output  logic [`SCR1_IMEM_AWIDTH-1:0]   port1_addr,
    input   logic [`SCR1_IMEM_DWIDTH-1:0]   port1_rdata,
    input   logic [1:0]                     port1_resp
);
 
//-------------------------------------------------------------------------------
// Local types declaration
//-------------------------------------------------------------------------------
typedef enum logic {
    SCR1_FSM_ADDR,
    SCR1_FSM_DATA
} type_scr1_fsm_e;
 
//-------------------------------------------------------------------------------
// Local signal declaration
//-------------------------------------------------------------------------------
type_scr1_fsm_e                 fsm;
logic                           port_sel;
logic                           port_sel_r;
logic [`SCR1_IMEM_DWIDTH-1:0]   sel_rdata;
logic [1:0]                     sel_resp;
logic                           sel_req_ack;
 
//-------------------------------------------------------------------------------
// FSM
//-------------------------------------------------------------------------------
assign port_sel = ((imem_addr & SCR1_ADDR_MASK) == SCR1_ADDR_PATTERN);
 
always_ff @(negedge rst_n, posedge clk) begin
    if (~rst_n) begin
        fsm        <= SCR1_FSM_ADDR;
        port_sel_r <= 1'b0;
    end else begin
        case (fsm)
            SCR1_FSM_ADDR : begin
                if (imem_req & sel_req_ack) begin
                    fsm <= SCR1_FSM_DATA;
                    port_sel_r <= port_sel;
                end
            end
            SCR1_FSM_DATA : begin
                case (sel_resp)
                    SCR1_MEM_RESP_RDY_OK : begin
                        if (imem_req & sel_req_ack) begin
                            fsm <= SCR1_FSM_DATA;
                            port_sel_r <= port_sel;
                        end else begin
                            fsm <= SCR1_FSM_ADDR;
                        end
                    end
                    SCR1_MEM_RESP_RDY_ER : begin
                        fsm <= SCR1_FSM_ADDR;
                    end
                    default : begin
                    end
                endcase
            end
            default : begin
            end
        endcase
    end
end
 
always_comb begin
    if ((fsm == SCR1_FSM_ADDR) | ((fsm == SCR1_FSM_DATA) & (sel_resp == SCR1_MEM_RESP_RDY_OK))) begin
        sel_req_ack = (port_sel) ? port1_req_ack : port0_req_ack;
    end else begin
        sel_req_ack = 1'b0;
    end
end
 
assign sel_rdata = (port_sel_r) ? port1_rdata : port0_rdata;
assign sel_resp  = (port_sel_r) ? port1_resp  : port0_resp;
 
//-------------------------------------------------------------------------------
// Interface to core
//-------------------------------------------------------------------------------
assign imem_req_ack = sel_req_ack;
assign imem_rdata   = sel_rdata;
assign imem_resp    = sel_resp;
 
//-------------------------------------------------------------------------------
// Interface to PORT0
//-------------------------------------------------------------------------------
always_comb begin
    port0_req = 1'b0;
    case (fsm)
        SCR1_FSM_ADDR : begin
            port0_req = imem_req & ~port_sel;
        end
        SCR1_FSM_DATA : begin
            if (sel_resp == SCR1_MEM_RESP_RDY_OK) begin
                port0_req = imem_req & ~port_sel;
            end
        end
        default : begin
        end
    endcase
end
 
`ifdef SCR1_XPROP_EN
assign port0_cmd   = (~port_sel) ? imem_cmd  : SCR1_MEM_CMD_ERROR;
assign port0_addr  = (~port_sel) ? imem_addr : 'x;
`else // SCR1_XPROP_EN
assign port0_cmd   = imem_cmd ;
assign port0_addr  = imem_addr;
`endif // SCR1_XPROP_EN
 
//-------------------------------------------------------------------------------
// Interface to PORT1
//-------------------------------------------------------------------------------
always_comb begin
    port1_req = 1'b0;
    case (fsm)
        SCR1_FSM_ADDR : begin
            port1_req = imem_req & port_sel;
        end
        SCR1_FSM_DATA : begin
            if (sel_resp == SCR1_MEM_RESP_RDY_OK) begin
                port1_req = imem_req & port_sel;
            end
        end
        default : begin
        end
    endcase
end
 
`ifdef SCR1_XPROP_EN
assign port1_cmd   = (port_sel) ? imem_cmd  : SCR1_MEM_CMD_ERROR;
assign port1_addr  = (port_sel) ? imem_addr : 'x;
`else // SCR1_XPROP_EN
assign port1_cmd   = imem_cmd ;
assign port1_addr  = imem_addr;
`endif // SCR1_XPROP_EN
 
`ifdef SCR1_TRGT_SIMULATION
//-------------------------------------------------------------------------------
// Assertion
//-------------------------------------------------------------------------------
 
SCR1_SVA_IMEM_RT_XCHECK : assert property (
    @(negedge clk) disable iff (~rst_n)
    imem_req |-> !$isunknown({port_sel, imem_cmd})
    ) else $error("IMEM router Error: unknown values");
 
`endif // SCR1_TRGT_SIMULATION
 
endmodule : scr1_imem_router

Line No.	Rev	Author	Line
1	11	dinesha	`/// Copyright by Syntacore LLC © 2016-2021. See LICENSE for details`
2			`/// @file`
3			`/// @brief Instruction memory router`
4			`///`
5			`include "scr1_memif.svh"
6			`include "scr1_arch_description.svh"
7
8			`module scr1_imem_router`
9			`#(`
10			parameter SCR1_ADDR_MASK = `SCR1_IMEM_AWIDTH'hFFFF0000,
11			parameter SCR1_ADDR_PATTERN = `SCR1_IMEM_AWIDTH'h00010000
12			`)`
13			`(`
14			`// Control signals`
15			`input logic rst_n,`
16			`input logic clk,`
17
18			`// Core interface`
19			`output logic imem_req_ack,`
20			`input logic imem_req,`
21	21	dinesha	`input logic imem_cmd,`
22	11	dinesha	input logic [`SCR1_IMEM_AWIDTH-1:0] imem_addr,
23			output logic [`SCR1_IMEM_DWIDTH-1:0] imem_rdata,
24	21	dinesha	`output logic [1:0] imem_resp,`
25	11	dinesha
26			`// PORT0 interface`
27			`input logic port0_req_ack,`
28			`output logic port0_req,`
29	21	dinesha	`output logic port0_cmd,`
30	11	dinesha	output logic [`SCR1_IMEM_AWIDTH-1:0] port0_addr,
31			input logic [`SCR1_IMEM_DWIDTH-1:0] port0_rdata,
32	21	dinesha	`input logic [1:0] port0_resp,`
33	11	dinesha
34			`// PORT1 interface`
35			`input logic port1_req_ack,`
36			`output logic port1_req,`
37	21	dinesha	`output logic port1_cmd,`
38	11	dinesha	output logic [`SCR1_IMEM_AWIDTH-1:0] port1_addr,
39			input logic [`SCR1_IMEM_DWIDTH-1:0] port1_rdata,
40	21	dinesha	`input logic [1:0] port1_resp`
41	11	dinesha	`);`
42
43			`//-------------------------------------------------------------------------------`
44			`// Local types declaration`
45			`//-------------------------------------------------------------------------------`
46			`typedef enum logic {`
47			`SCR1_FSM_ADDR,`
48			`SCR1_FSM_DATA`
49			`} type_scr1_fsm_e;`
50
51			`//-------------------------------------------------------------------------------`
52			`// Local signal declaration`
53			`//-------------------------------------------------------------------------------`
54			`type_scr1_fsm_e fsm;`
55			`logic port_sel;`
56			`logic port_sel_r;`
57			logic [`SCR1_IMEM_DWIDTH-1:0] sel_rdata;
58	21	dinesha	`logic [1:0] sel_resp;`
59	11	dinesha	`logic sel_req_ack;`
60
61			`//-------------------------------------------------------------------------------`
62			`// FSM`
63			`//-------------------------------------------------------------------------------`
64			`assign port_sel = ((imem_addr & SCR1_ADDR_MASK) == SCR1_ADDR_PATTERN);`
65
66			`always_ff @(negedge rst_n, posedge clk) begin`
67			`if (~rst_n) begin`
68			`fsm <= SCR1_FSM_ADDR;`
69			`port_sel_r <= 1'b0;`
70			`end else begin`
71			`case (fsm)`
72			`SCR1_FSM_ADDR : begin`
73			`if (imem_req & sel_req_ack) begin`
74			`fsm <= SCR1_FSM_DATA;`
75			`port_sel_r <= port_sel;`
76			`end`
77			`end`
78			`SCR1_FSM_DATA : begin`
79			`case (sel_resp)`
80			`SCR1_MEM_RESP_RDY_OK : begin`
81			`if (imem_req & sel_req_ack) begin`
82			`fsm <= SCR1_FSM_DATA;`
83			`port_sel_r <= port_sel;`
84			`end else begin`
85			`fsm <= SCR1_FSM_ADDR;`
86			`end`
87			`end`
88			`SCR1_MEM_RESP_RDY_ER : begin`
89			`fsm <= SCR1_FSM_ADDR;`
90			`end`
91			`default : begin`
92			`end`
93			`endcase`
94			`end`
95			`default : begin`
96			`end`
97			`endcase`
98			`end`
99			`end`
100
101			`always_comb begin`
102			`if ((fsm == SCR1_FSM_ADDR) \| ((fsm == SCR1_FSM_DATA) & (sel_resp == SCR1_MEM_RESP_RDY_OK))) begin`
103			`sel_req_ack = (port_sel) ? port1_req_ack : port0_req_ack;`
104			`end else begin`
105			`sel_req_ack = 1'b0;`
106			`end`
107			`end`
108
109			`assign sel_rdata = (port_sel_r) ? port1_rdata : port0_rdata;`
110			`assign sel_resp = (port_sel_r) ? port1_resp : port0_resp;`
111
112			`//-------------------------------------------------------------------------------`
113			`// Interface to core`
114			`//-------------------------------------------------------------------------------`
115			`assign imem_req_ack = sel_req_ack;`
116			`assign imem_rdata = sel_rdata;`
117			`assign imem_resp = sel_resp;`
118
119			`//-------------------------------------------------------------------------------`
120			`// Interface to PORT0`
121			`//-------------------------------------------------------------------------------`
122			`always_comb begin`
123			`port0_req = 1'b0;`
124			`case (fsm)`
125			`SCR1_FSM_ADDR : begin`
126			`port0_req = imem_req & ~port_sel;`
127			`end`
128			`SCR1_FSM_DATA : begin`
129			`if (sel_resp == SCR1_MEM_RESP_RDY_OK) begin`
130			`port0_req = imem_req & ~port_sel;`
131			`end`
132			`end`
133			`default : begin`
134			`end`
135			`endcase`
136			`end`
137
138			`ifdef SCR1_XPROP_EN
139			`assign port0_cmd = (~port_sel) ? imem_cmd : SCR1_MEM_CMD_ERROR;`
140			`assign port0_addr = (~port_sel) ? imem_addr : 'x;`
141			`else // SCR1_XPROP_EN
142			`assign port0_cmd = imem_cmd ;`
143			`assign port0_addr = imem_addr;`
144			`endif // SCR1_XPROP_EN
145
146			`//-------------------------------------------------------------------------------`
147			`// Interface to PORT1`
148			`//-------------------------------------------------------------------------------`
149			`always_comb begin`
150			`port1_req = 1'b0;`
151			`case (fsm)`
152			`SCR1_FSM_ADDR : begin`
153			`port1_req = imem_req & port_sel;`
154			`end`
155			`SCR1_FSM_DATA : begin`
156			`if (sel_resp == SCR1_MEM_RESP_RDY_OK) begin`
157			`port1_req = imem_req & port_sel;`
158			`end`
159			`end`
160			`default : begin`
161			`end`
162			`endcase`
163			`end`
164
165			`ifdef SCR1_XPROP_EN
166			`assign port1_cmd = (port_sel) ? imem_cmd : SCR1_MEM_CMD_ERROR;`
167			`assign port1_addr = (port_sel) ? imem_addr : 'x;`
168			`else // SCR1_XPROP_EN
169			`assign port1_cmd = imem_cmd ;`
170			`assign port1_addr = imem_addr;`
171			`endif // SCR1_XPROP_EN
172
173			`ifdef SCR1_TRGT_SIMULATION
174			`//-------------------------------------------------------------------------------`
175			`// Assertion`
176			`//-------------------------------------------------------------------------------`
177
178			`SCR1_SVA_IMEM_RT_XCHECK : assert property (`
179			`@(negedge clk) disable iff (~rst_n)`
180			`imem_req \|-> !$isunknown({port_sel, imem_cmd})`
181			`) else $error("IMEM router Error: unknown values");`
182
183			`endif // SCR1_TRGT_SIMULATION
184
185			`endmodule : scr1_imem_router`

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[/] [yifive/] [trunk/] [caravel_yifive/] [verilog/] [rtl/] [syntacore/] [scr1/] [src/] [top/] [scr1_imem_router.sv] - Blame information for rev 21