1 |
11 |
dinesha |
//////////////////////////////////////////////////////////////////////
|
2 |
|
|
//// ////
|
3 |
|
|
//// yifive Wishbone interface for Instruction memory ////
|
4 |
|
|
//// ////
|
5 |
|
|
//// This file is part of the yifive cores project ////
|
6 |
|
|
//// http://www.opencores.org/cores/yifive/ ////
|
7 |
|
|
//// ////
|
8 |
|
|
//// Description: ////
|
9 |
|
|
//// integrated wishbone i/f to instruction memory ////
|
10 |
|
|
//// ////
|
11 |
|
|
//// To Do: ////
|
12 |
|
|
//// nothing ////
|
13 |
|
|
//// ////
|
14 |
|
|
//// Author(s): ////
|
15 |
|
|
//// - Dinesh Annayya, dinesha@opencores.org ////
|
16 |
|
|
//// ////
|
17 |
|
|
//// Revision : ////
|
18 |
|
|
//// v0: June 7, 2021, Dinesh A ////
|
19 |
|
|
//// wishbone integration ////
|
20 |
21 |
dinesha |
//// v1: June 9, 2021, Dinesh A ////
|
21 |
|
|
//// On power up, wishbone output are unkown as it ////
|
22 |
|
|
//// driven from fifo output. To avoid unknown ////
|
23 |
|
|
//// propgation, we are driving 'h0 when fifo empty ////
|
24 |
11 |
dinesha |
//// ////
|
25 |
|
|
//////////////////////////////////////////////////////////////////////
|
26 |
|
|
//// ////
|
27 |
|
|
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
|
28 |
|
|
//// ////
|
29 |
|
|
//// This source file may be used and distributed without ////
|
30 |
|
|
//// restriction provided that this copyright statement is not ////
|
31 |
|
|
//// removed from the file and that any derivative work contains ////
|
32 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
33 |
|
|
//// ////
|
34 |
|
|
//// This source file is free software; you can redistribute it ////
|
35 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
36 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
37 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
38 |
|
|
//// later version. ////
|
39 |
|
|
//// ////
|
40 |
|
|
//// This source is distributed in the hope that it will be ////
|
41 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
42 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
43 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
44 |
|
|
//// details. ////
|
45 |
|
|
//// ////
|
46 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
47 |
|
|
//// Public License along with this source; if not, download it ////
|
48 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
49 |
|
|
//// ////
|
50 |
|
|
//////////////////////////////////////////////////////////////////////
|
51 |
|
|
// Orginal owner Details ////
|
52 |
|
|
//////////////////////////////////////////////////////////////////////
|
53 |
|
|
/// Copyright by Syntacore LLC © 2016-2021. See LICENSE for details///
|
54 |
|
|
/// @file ///
|
55 |
|
|
/// @brief Instruction memory AHB bridge ///
|
56 |
|
|
//////////////////////////////////////////////////////////////////////
|
57 |
|
|
|
58 |
|
|
`include "scr1_wb.svh"
|
59 |
|
|
`include "scr1_memif.svh"
|
60 |
|
|
|
61 |
|
|
module scr1_imem_wb (
|
62 |
|
|
// Control Signals
|
63 |
|
|
input logic rst_n,
|
64 |
|
|
input logic clk,
|
65 |
|
|
|
66 |
|
|
// Core Interface
|
67 |
|
|
output logic imem_req_ack,
|
68 |
|
|
input logic imem_req,
|
69 |
|
|
input logic [SCR1_WB_WIDTH-1:0] imem_addr,
|
70 |
|
|
output logic [SCR1_WB_WIDTH-1:0] imem_rdata,
|
71 |
21 |
dinesha |
output logic [1:0] imem_resp,
|
72 |
11 |
dinesha |
|
73 |
|
|
// WB Interface
|
74 |
|
|
output logic wbd_stb_o, // strobe/request
|
75 |
|
|
output logic [SCR1_WB_WIDTH-1:0] wbd_adr_o, // address
|
76 |
|
|
output logic wbd_we_o, // write
|
77 |
|
|
output logic [SCR1_WB_WIDTH-1:0] wbd_dat_o, // data output
|
78 |
|
|
output logic [3:0] wbd_sel_o, // byte enable
|
79 |
|
|
input logic [SCR1_WB_WIDTH-1:0] wbd_dat_i, // data input
|
80 |
|
|
input logic wbd_ack_i, // acknowlegement
|
81 |
|
|
input logic wbd_err_i // error
|
82 |
|
|
|
83 |
|
|
);
|
84 |
|
|
|
85 |
|
|
//-------------------------------------------------------------------------------
|
86 |
|
|
// Local parameters declaration
|
87 |
|
|
//-------------------------------------------------------------------------------
|
88 |
|
|
`ifndef SCR1_IMEM_WB_OUT_BP
|
89 |
|
|
localparam SCR1_FIFO_WIDTH = 2;
|
90 |
|
|
localparam SCR1_FIFO_CNT_WIDTH = $clog2(SCR1_FIFO_WIDTH+1);
|
91 |
|
|
`endif // SCR1_IMEM_WB_OUT_BP
|
92 |
|
|
|
93 |
|
|
//-------------------------------------------------------------------------------
|
94 |
|
|
// Local types declaration
|
95 |
|
|
//-------------------------------------------------------------------------------
|
96 |
|
|
typedef enum logic {
|
97 |
|
|
SCR1_FSM_ADDR = 1'b0,
|
98 |
|
|
SCR1_FSM_DATA = 1'b1,
|
99 |
|
|
SCR1_FSM_ERR = 1'bx
|
100 |
|
|
} type_scr1_fsm_e;
|
101 |
|
|
|
102 |
|
|
typedef struct packed {
|
103 |
|
|
logic [SCR1_WB_WIDTH-1:0] haddr;
|
104 |
|
|
} type_scr1_req_fifo_s;
|
105 |
|
|
|
106 |
|
|
typedef struct packed {
|
107 |
|
|
logic hresp;
|
108 |
|
|
logic [SCR1_WB_WIDTH-1:0] hrdata;
|
109 |
|
|
} type_scr1_resp_fifo_s;
|
110 |
|
|
|
111 |
|
|
//-------------------------------------------------------------------------------
|
112 |
|
|
// Local signal declaration
|
113 |
|
|
//-------------------------------------------------------------------------------
|
114 |
|
|
type_scr1_fsm_e fsm;
|
115 |
|
|
logic req_fifo_rd;
|
116 |
|
|
logic req_fifo_wr;
|
117 |
|
|
logic req_fifo_up;
|
118 |
|
|
`ifdef SCR1_IMEM_WB_OUT_BP
|
119 |
|
|
type_scr1_req_fifo_s req_fifo_r;
|
120 |
|
|
type_scr1_req_fifo_s [0:0] req_fifo;
|
121 |
|
|
`else // SCR1_IMEM_WB_OUT_BP
|
122 |
|
|
logic [SCR1_WB_WIDTH-1:0] req_fifo_dout;
|
123 |
|
|
`endif // SCR1_IMEM_WB_OUT_BP
|
124 |
|
|
|
125 |
|
|
logic req_fifo_empty;
|
126 |
|
|
logic req_fifo_full;
|
127 |
|
|
|
128 |
|
|
type_scr1_resp_fifo_s resp_fifo;
|
129 |
|
|
logic resp_fifo_hready;
|
130 |
|
|
|
131 |
|
|
//-------------------------------------------------------------------------------
|
132 |
|
|
// Interface to Core
|
133 |
|
|
//-------------------------------------------------------------------------------
|
134 |
|
|
assign imem_req_ack = ~req_fifo_full;
|
135 |
|
|
assign req_fifo_wr = ~req_fifo_full & imem_req;
|
136 |
|
|
|
137 |
|
|
assign imem_rdata = resp_fifo.hrdata;
|
138 |
|
|
|
139 |
|
|
assign imem_resp = (resp_fifo_hready)
|
140 |
|
|
? (resp_fifo.hresp == 1'b1)
|
141 |
|
|
? SCR1_MEM_RESP_RDY_OK
|
142 |
|
|
: SCR1_MEM_RESP_RDY_ER
|
143 |
|
|
: SCR1_MEM_RESP_NOTRDY;
|
144 |
|
|
|
145 |
|
|
//-------------------------------------------------------------------------------
|
146 |
|
|
// REQ_FIFO
|
147 |
|
|
//-------------------------------------------------------------------------------
|
148 |
|
|
`ifdef SCR1_IMEM_WB_OUT_BP
|
149 |
|
|
always_ff @(negedge rst_n, posedge clk) begin
|
150 |
|
|
if (~rst_n) begin
|
151 |
|
|
req_fifo_full <= 1'b0;
|
152 |
|
|
end else begin
|
153 |
|
|
if (~req_fifo_full) begin
|
154 |
|
|
req_fifo_full <= imem_req & ~req_fifo_rd;
|
155 |
|
|
end else begin
|
156 |
|
|
req_fifo_full <= ~req_fifo_rd;
|
157 |
|
|
end
|
158 |
|
|
end
|
159 |
|
|
end
|
160 |
|
|
assign req_fifo_empty = ~(req_fifo_full | imem_req);
|
161 |
|
|
|
162 |
|
|
assign req_fifo_up = ~req_fifo_rd & req_fifo_wr;
|
163 |
|
|
always_ff @(posedge clk) begin
|
164 |
|
|
if (req_fifo_up) begin
|
165 |
|
|
req_fifo_r.haddr <= imem_addr;
|
166 |
|
|
end
|
167 |
|
|
end
|
168 |
|
|
|
169 |
|
|
assign req_fifo[0] = (req_fifo_full) ? req_fifo_r : imem_addr;
|
170 |
|
|
|
171 |
|
|
`else // SCR1_IMEM_WB_OUT_BP
|
172 |
|
|
|
173 |
|
|
|
174 |
|
|
sync_fifo #(
|
175 |
19 |
dinesha |
.W(SCR1_WB_WIDTH), // Data Width
|
176 |
|
|
.D(2) // FIFO DEPTH
|
177 |
11 |
dinesha |
) u_req_fifo(
|
178 |
|
|
|
179 |
19 |
dinesha |
.rd_data (req_fifo_dout ),
|
180 |
11 |
dinesha |
|
181 |
19 |
dinesha |
.reset_n (rst_n ),
|
182 |
11 |
dinesha |
.clk (clk ),
|
183 |
|
|
.wr_en (req_fifo_wr ), // Write
|
184 |
|
|
.rd_en (req_fifo_rd ), // Read
|
185 |
19 |
dinesha |
.wr_data (imem_addr ),
|
186 |
11 |
dinesha |
.full (req_fifo_full ),
|
187 |
|
|
.empty (req_fifo_empty )
|
188 |
|
|
);
|
189 |
|
|
|
190 |
|
|
|
191 |
|
|
|
192 |
|
|
|
193 |
|
|
`endif // SCR1_IMEM_WB_OUT_BP
|
194 |
|
|
|
195 |
|
|
|
196 |
|
|
always_comb begin
|
197 |
|
|
req_fifo_rd = 1'b0;
|
198 |
|
|
if (wbd_ack_i) begin
|
199 |
|
|
req_fifo_rd = ~req_fifo_empty;
|
200 |
|
|
end
|
201 |
|
|
end
|
202 |
|
|
|
203 |
|
|
//-------------------------------------------------------------------------------
|
204 |
|
|
// FIFO response
|
205 |
|
|
//-------------------------------------------------------------------------------
|
206 |
|
|
`ifdef SCR1_IMEM_WB_IN_BP
|
207 |
|
|
assign resp_fifo_hready = wbd_ack_i;
|
208 |
|
|
assign resp_fifo.hresp = (wbd_err_i) ? 1'b0 : 1'b1;
|
209 |
|
|
assign resp_fifo.hrdata = wbd_dat_i;
|
210 |
|
|
assign wbd_stb_o = ~req_fifo_empty;
|
211 |
|
|
assign wbd_adr_o = req_fifo[0];
|
212 |
|
|
assign wbd_we_o = 0; // Only Read supported
|
213 |
|
|
assign wbd_dat_o = 32'h0; // No Write
|
214 |
|
|
assign wbd_sel_o = 4'b1111; // Only Read allowed in imem i/f
|
215 |
|
|
|
216 |
|
|
|
217 |
|
|
`else // SCR1_IMEM_WB_IN_BP
|
218 |
|
|
always_ff @(negedge rst_n, posedge clk) begin
|
219 |
|
|
if (~rst_n) begin
|
220 |
|
|
resp_fifo_hready <= 1'b0;
|
221 |
|
|
end else begin
|
222 |
|
|
resp_fifo_hready <= wbd_ack_i ;
|
223 |
|
|
end
|
224 |
|
|
end
|
225 |
|
|
|
226 |
|
|
always_ff @(posedge clk) begin
|
227 |
|
|
if (wbd_ack_i) begin
|
228 |
|
|
resp_fifo.hresp <= (wbd_err_i) ? 1'b0 : 1'b1;
|
229 |
|
|
resp_fifo.hrdata <= wbd_dat_i;
|
230 |
|
|
end
|
231 |
|
|
end
|
232 |
|
|
|
233 |
|
|
assign wbd_stb_o = ~req_fifo_empty;
|
234 |
21 |
dinesha |
// On Power, to avoid unknow propgating the value
|
235 |
|
|
assign wbd_adr_o = (req_fifo_empty) ? 'h0 : req_fifo_dout;
|
236 |
11 |
dinesha |
assign wbd_we_o = 0; // Only Read supported
|
237 |
|
|
assign wbd_dat_o = 32'h0; // No Write
|
238 |
|
|
assign wbd_sel_o = 4'b1111; // Only Read allowed in imem i/f
|
239 |
|
|
`endif // SCR1_IMEM_WB_IN_BP
|
240 |
|
|
|
241 |
|
|
|
242 |
|
|
|
243 |
|
|
`ifdef SCR1_TRGT_SIMULATION
|
244 |
|
|
//-------------------------------------------------------------------------------
|
245 |
|
|
// Assertion
|
246 |
|
|
//-------------------------------------------------------------------------------
|
247 |
|
|
|
248 |
|
|
// Check Core interface
|
249 |
|
|
SCR1_SVA_IMEM_WB_BRIDGE_REQ_XCHECK : assert property (
|
250 |
|
|
@(negedge clk) disable iff (~rst_n)
|
251 |
|
|
!$isunknown(imem_req)
|
252 |
|
|
) else $error("IMEM WB bridge Error: imem_req has unknown values");
|
253 |
|
|
|
254 |
|
|
SCR1_IMEM_WB_BRIDGE_ADDR_XCHECK : assert property (
|
255 |
|
|
@(negedge clk) disable iff (~rst_n)
|
256 |
|
|
imem_req |-> !$isunknown(imem_addr)
|
257 |
|
|
) else $error("IMEM WB bridge Error: imem_addr has unknown values");
|
258 |
|
|
|
259 |
|
|
SCR1_IMEM_WB_BRIDGE_ADDR_ALLIGN : assert property (
|
260 |
|
|
@(negedge clk) disable iff (~rst_n)
|
261 |
|
|
imem_req |-> (imem_addr[1:0] == '0)
|
262 |
|
|
) else $error("IMEM WB bridge Error: imem_addr has unalign values");
|
263 |
|
|
|
264 |
|
|
// Check WB interface
|
265 |
|
|
SCR1_IMEM_WB_BRIDGE_HREADY_XCHECK : assert property (
|
266 |
|
|
@(negedge clk) disable iff (~rst_n)
|
267 |
|
|
!$isunknown(hready)
|
268 |
|
|
) else $error("IMEM WB bridge Error: hready has unknown values");
|
269 |
|
|
|
270 |
|
|
SCR1_IMEM_WB_BRIDGE_HRESP_XCHECK : assert property (
|
271 |
|
|
@(negedge clk) disable iff (~rst_n)
|
272 |
|
|
!$isunknown(hresp)
|
273 |
|
|
) else $error("IMEM WB bridge Error: hresp has unknown values");
|
274 |
|
|
|
275 |
|
|
`endif // SCR1_TRGT_SIMULATION
|
276 |
|
|
|
277 |
|
|
endmodule : scr1_imem_wb
|