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dinesha |
/// Copyright by Syntacore LLC © 2016-2020. See LICENSE for details
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/// @file
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/// @brief SCR1 AXI top
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///
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`include "scr1_arch_description.svh"
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`include "scr1_memif.svh"
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`ifdef SCR1_IPIC_EN
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`include "scr1_ipic.svh"
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`endif // SCR1_IPIC_EN
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`ifdef SCR1_TCM_EN
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`define SCR1_IMEM_ROUTER_EN
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`endif // SCR1_TCM_EN
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module scr1_top_axi (
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// Control
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input logic pwrup_rst_n, // Power-Up Reset
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input logic rst_n, // Regular Reset signal
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input logic cpu_rst_n, // CPU Reset (Core Reset)
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input logic test_mode, // Test mode
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input logic test_rst_n, // Test mode's reset
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input logic clk, // System clock
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input logic rtc_clk, // Real-time clock
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`ifdef SCR1_DBG_EN
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output logic sys_rst_n_o, // External System Reset output
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// (for the processor cluster's components or
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// external SOC (could be useful in small
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// SCR-core-centric SOCs))
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output logic sys_rdc_qlfy_o, // System-to-External SOC Reset Domain Crossing Qualifier
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`endif // SCR1_DBG_EN
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// Fuses
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input logic [`SCR1_XLEN-1:0] fuse_mhartid, // Hart ID
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`ifdef SCR1_DBG_EN
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input logic [31:0] fuse_idcode, // TAPC IDCODE
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`endif // SCR1_DBG_EN
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// IRQ
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`ifdef SCR1_IPIC_EN
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input logic [SCR1_IRQ_LINES_NUM-1:0] irq_lines, // IRQ lines to IPIC
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`else // SCR1_IPIC_EN
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input logic ext_irq, // External IRQ input
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`endif // SCR1_IPIC_EN
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input logic soft_irq, // Software IRQ input
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`ifdef SCR1_DBG_EN
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// -- JTAG I/F
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input logic trst_n,
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input logic tck,
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input logic tms,
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input logic tdi,
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output logic tdo,
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output logic tdo_en,
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`endif // SCR1_DBG_EN
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// Instruction Memory Interface
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output logic [3:0] io_axi_imem_awid,
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output logic [31:0] io_axi_imem_awaddr,
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output logic [7:0] io_axi_imem_awlen,
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output logic [2:0] io_axi_imem_awsize,
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output logic [1:0] io_axi_imem_awburst,
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output logic io_axi_imem_awlock,
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output logic [3:0] io_axi_imem_awcache,
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output logic [2:0] io_axi_imem_awprot,
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output logic [3:0] io_axi_imem_awregion,
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output logic [3:0] io_axi_imem_awuser,
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output logic [3:0] io_axi_imem_awqos,
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output logic io_axi_imem_awvalid,
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input logic io_axi_imem_awready,
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output logic [31:0] io_axi_imem_wdata,
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output logic [3:0] io_axi_imem_wstrb,
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output logic io_axi_imem_wlast,
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output logic [3:0] io_axi_imem_wuser,
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output logic io_axi_imem_wvalid,
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input logic io_axi_imem_wready,
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input logic [3:0] io_axi_imem_bid,
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input logic [1:0] io_axi_imem_bresp,
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input logic io_axi_imem_bvalid,
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input logic [3:0] io_axi_imem_buser,
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output logic io_axi_imem_bready,
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output logic [3:0] io_axi_imem_arid,
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output logic [31:0] io_axi_imem_araddr,
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output logic [7:0] io_axi_imem_arlen,
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output logic [2:0] io_axi_imem_arsize,
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output logic [1:0] io_axi_imem_arburst,
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output logic io_axi_imem_arlock,
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output logic [3:0] io_axi_imem_arcache,
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output logic [2:0] io_axi_imem_arprot,
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output logic [3:0] io_axi_imem_arregion,
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output logic [3:0] io_axi_imem_aruser,
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output logic [3:0] io_axi_imem_arqos,
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output logic io_axi_imem_arvalid,
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input logic io_axi_imem_arready,
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input logic [3:0] io_axi_imem_rid,
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input logic [31:0] io_axi_imem_rdata,
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input logic [1:0] io_axi_imem_rresp,
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input logic io_axi_imem_rlast,
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input logic [3:0] io_axi_imem_ruser,
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input logic io_axi_imem_rvalid,
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output logic io_axi_imem_rready,
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// Data Memory Interface
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output logic [3:0] io_axi_dmem_awid,
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output logic [31:0] io_axi_dmem_awaddr,
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output logic [7:0] io_axi_dmem_awlen,
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output logic [2:0] io_axi_dmem_awsize,
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output logic [1:0] io_axi_dmem_awburst,
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output logic io_axi_dmem_awlock,
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output logic [3:0] io_axi_dmem_awcache,
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output logic [2:0] io_axi_dmem_awprot,
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output logic [3:0] io_axi_dmem_awregion,
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output logic [3:0] io_axi_dmem_awuser,
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output logic [3:0] io_axi_dmem_awqos,
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output logic io_axi_dmem_awvalid,
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input logic io_axi_dmem_awready,
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output logic [31:0] io_axi_dmem_wdata,
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output logic [3:0] io_axi_dmem_wstrb,
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output logic io_axi_dmem_wlast,
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output logic [3:0] io_axi_dmem_wuser,
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output logic io_axi_dmem_wvalid,
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input logic io_axi_dmem_wready,
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input logic [3:0] io_axi_dmem_bid,
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input logic [1:0] io_axi_dmem_bresp,
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input logic io_axi_dmem_bvalid,
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input logic [3:0] io_axi_dmem_buser,
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output logic io_axi_dmem_bready,
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output logic [3:0] io_axi_dmem_arid,
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output logic [31:0] io_axi_dmem_araddr,
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output logic [7:0] io_axi_dmem_arlen,
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output logic [2:0] io_axi_dmem_arsize,
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output logic [1:0] io_axi_dmem_arburst,
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output logic io_axi_dmem_arlock,
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output logic [3:0] io_axi_dmem_arcache,
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output logic [2:0] io_axi_dmem_arprot,
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output logic [3:0] io_axi_dmem_arregion,
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output logic [3:0] io_axi_dmem_aruser,
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output logic [3:0] io_axi_dmem_arqos,
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output logic io_axi_dmem_arvalid,
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input logic io_axi_dmem_arready,
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input logic [3:0] io_axi_dmem_rid,
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input logic [31:0] io_axi_dmem_rdata,
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input logic [1:0] io_axi_dmem_rresp,
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input logic io_axi_dmem_rlast,
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input logic [3:0] io_axi_dmem_ruser,
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input logic io_axi_dmem_rvalid,
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output logic io_axi_dmem_rready
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);
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//-------------------------------------------------------------------------------
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// Local parameters
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//-------------------------------------------------------------------------------
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localparam int unsigned SCR1_CLUSTER_TOP_RST_SYNC_STAGES_NUM = 2;
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//-------------------------------------------------------------------------------
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// Local signal declaration
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//-------------------------------------------------------------------------------
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// Reset logic
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logic pwrup_rst_n_sync;
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logic rst_n_sync;
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logic cpu_rst_n_sync;
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logic core_rst_n_local;
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logic axi_rst_n;
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`ifdef SCR1_DBG_EN
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logic tapc_trst_n;
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`endif // SCR1_DBG_EN
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// Instruction memory interface from core to router
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logic core_imem_req_ack;
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logic core_imem_req;
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type_scr1_mem_cmd_e core_imem_cmd;
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logic [`SCR1_IMEM_AWIDTH-1:0] core_imem_addr;
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logic [`SCR1_IMEM_DWIDTH-1:0] core_imem_rdata;
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type_scr1_mem_resp_e core_imem_resp;
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// Data memory interface from core to router
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logic core_dmem_req_ack;
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logic core_dmem_req;
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type_scr1_mem_cmd_e core_dmem_cmd;
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type_scr1_mem_width_e core_dmem_width;
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logic [`SCR1_DMEM_AWIDTH-1:0] core_dmem_addr;
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logic [`SCR1_DMEM_DWIDTH-1:0] core_dmem_wdata;
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logic [`SCR1_DMEM_DWIDTH-1:0] core_dmem_rdata;
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type_scr1_mem_resp_e core_dmem_resp;
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// Instruction memory interface from router to AXI bridge
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logic axi_imem_req_ack;
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logic axi_imem_req;
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type_scr1_mem_cmd_e axi_imem_cmd;
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logic [`SCR1_IMEM_AWIDTH-1:0] axi_imem_addr;
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logic [`SCR1_IMEM_DWIDTH-1:0] axi_imem_rdata;
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type_scr1_mem_resp_e axi_imem_resp;
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// Data memory interface from router to AXI bridge
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logic axi_dmem_req_ack;
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logic axi_dmem_req;
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type_scr1_mem_cmd_e axi_dmem_cmd;
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type_scr1_mem_width_e axi_dmem_width;
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logic [`SCR1_DMEM_AWIDTH-1:0] axi_dmem_addr;
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logic [`SCR1_DMEM_DWIDTH-1:0] axi_dmem_wdata;
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logic [`SCR1_DMEM_DWIDTH-1:0] axi_dmem_rdata;
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type_scr1_mem_resp_e axi_dmem_resp;
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`ifdef SCR1_TCM_EN
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// Instruction memory interface from router to TCM
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logic tcm_imem_req_ack;
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logic tcm_imem_req;
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type_scr1_mem_cmd_e tcm_imem_cmd;
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logic [`SCR1_IMEM_AWIDTH-1:0] tcm_imem_addr;
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logic [`SCR1_IMEM_DWIDTH-1:0] tcm_imem_rdata;
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type_scr1_mem_resp_e tcm_imem_resp;
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// Data memory interface from router to TCM
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logic tcm_dmem_req_ack;
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logic tcm_dmem_req;
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type_scr1_mem_cmd_e tcm_dmem_cmd;
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type_scr1_mem_width_e tcm_dmem_width;
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logic [`SCR1_DMEM_AWIDTH-1:0] tcm_dmem_addr;
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logic [`SCR1_DMEM_DWIDTH-1:0] tcm_dmem_wdata;
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logic [`SCR1_DMEM_DWIDTH-1:0] tcm_dmem_rdata;
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type_scr1_mem_resp_e tcm_dmem_resp;
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`endif // SCR1_TCM_EN
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// Data memory interface from router to memory-mapped timer
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logic timer_dmem_req_ack;
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logic timer_dmem_req;
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type_scr1_mem_cmd_e timer_dmem_cmd;
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type_scr1_mem_width_e timer_dmem_width;
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logic [`SCR1_DMEM_AWIDTH-1:0] timer_dmem_addr;
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logic [`SCR1_DMEM_DWIDTH-1:0] timer_dmem_wdata;
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logic [`SCR1_DMEM_DWIDTH-1:0] timer_dmem_rdata;
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type_scr1_mem_resp_e timer_dmem_resp;
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// Misc
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logic timer_irq;
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logic [63:0] timer_val;
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logic axi_reinit;
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logic axi_imem_idle;
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logic axi_dmem_idle;
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//-------------------------------------------------------------------------------
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// Reset logic
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//-------------------------------------------------------------------------------
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// Power-Up Reset synchronizer
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scr1_reset_sync_cell #(
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.STAGES_AMOUNT (SCR1_CLUSTER_TOP_RST_SYNC_STAGES_NUM)
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) i_pwrup_rstn_reset_sync (
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.rst_n (pwrup_rst_n ),
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.clk (clk ),
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.test_rst_n (test_rst_n ),
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.test_mode (test_mode ),
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.rst_n_in (1'b1 ),
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.rst_n_out (pwrup_rst_n_sync)
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);
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// Regular Reset synchronizer
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scr1_reset_sync_cell #(
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.STAGES_AMOUNT (SCR1_CLUSTER_TOP_RST_SYNC_STAGES_NUM)
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) i_rstn_reset_sync (
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.rst_n (pwrup_rst_n ),
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.clk (clk ),
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.test_rst_n (test_rst_n ),
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.test_mode (test_mode ),
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.rst_n_in (rst_n ),
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.rst_n_out (rst_n_sync )
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);
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// CPU Reset synchronizer
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scr1_reset_sync_cell #(
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.STAGES_AMOUNT (SCR1_CLUSTER_TOP_RST_SYNC_STAGES_NUM)
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) i_cpu_rstn_reset_sync (
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.rst_n (pwrup_rst_n ),
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.clk (clk ),
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.test_rst_n (test_rst_n ),
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.test_mode (test_mode ),
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.rst_n_in (cpu_rst_n ),
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.rst_n_out (cpu_rst_n_sync )
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);
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`ifdef SCR1_DBG_EN
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// TAPC Reset
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scr1_reset_and2_cell i_tapc_rstn_and2_cell (
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.rst_n_in ({trst_n, pwrup_rst_n}),
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.test_rst_n (test_rst_n ),
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.test_mode (test_mode ),
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.rst_n_out (tapc_trst_n )
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);
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`endif // SCR1_DBG_EN
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`ifdef SCR1_DBG_EN
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|
|
assign axi_rst_n = sys_rst_n_o;
|
| 292 |
|
|
`else // SCR1_DBG_EN
|
| 293 |
|
|
assign axi_rst_n = rst_n_sync;
|
| 294 |
|
|
`endif // SCR1_DBG_EN
|
| 295 |
|
|
|
| 296 |
|
|
//-------------------------------------------------------------------------------
|
| 297 |
|
|
// SCR1 core instance
|
| 298 |
|
|
//-------------------------------------------------------------------------------
|
| 299 |
|
|
scr1_core_top i_core_top (
|
| 300 |
|
|
// Common
|
| 301 |
|
|
.pwrup_rst_n (pwrup_rst_n_sync ),
|
| 302 |
|
|
.rst_n (rst_n_sync ),
|
| 303 |
|
|
.cpu_rst_n (cpu_rst_n_sync ),
|
| 304 |
|
|
.test_mode (test_mode ),
|
| 305 |
|
|
.test_rst_n (test_rst_n ),
|
| 306 |
|
|
.clk (clk ),
|
| 307 |
|
|
.core_rst_n_o (core_rst_n_local ),
|
| 308 |
|
|
.core_rdc_qlfy_o ( ),
|
| 309 |
|
|
`ifdef SCR1_DBG_EN
|
| 310 |
|
|
.sys_rst_n_o (sys_rst_n_o ),
|
| 311 |
|
|
.sys_rdc_qlfy_o (sys_rdc_qlfy_o ),
|
| 312 |
|
|
`endif // SCR1_DBG_EN
|
| 313 |
|
|
|
| 314 |
|
|
// Fuses
|
| 315 |
|
|
.core_fuse_mhartid_i (fuse_mhartid ),
|
| 316 |
|
|
`ifdef SCR1_DBG_EN
|
| 317 |
|
|
.tapc_fuse_idcode_i (fuse_idcode ),
|
| 318 |
|
|
`endif // SCR1_DBG_EN
|
| 319 |
|
|
|
| 320 |
|
|
// IRQ
|
| 321 |
|
|
`ifdef SCR1_IPIC_EN
|
| 322 |
|
|
.core_irq_lines_i (irq_lines ),
|
| 323 |
|
|
`else // SCR1_IPIC_EN
|
| 324 |
|
|
.core_irq_ext_i (ext_irq ),
|
| 325 |
|
|
`endif // SCR1_IPIC_EN
|
| 326 |
|
|
.core_irq_soft_i (soft_irq ),
|
| 327 |
|
|
.core_irq_mtimer_i (timer_irq ),
|
| 328 |
|
|
|
| 329 |
|
|
// Memory-mapped external timer
|
| 330 |
|
|
.core_mtimer_val_i (timer_val ),
|
| 331 |
|
|
|
| 332 |
|
|
`ifdef SCR1_DBG_EN
|
| 333 |
|
|
// Debug interface
|
| 334 |
|
|
.tapc_trst_n (tapc_trst_n ),
|
| 335 |
|
|
.tapc_tck (tck ),
|
| 336 |
|
|
.tapc_tms (tms ),
|
| 337 |
|
|
.tapc_tdi (tdi ),
|
| 338 |
|
|
.tapc_tdo (tdo ),
|
| 339 |
|
|
.tapc_tdo_en (tdo_en ),
|
| 340 |
|
|
`endif // SCR1_DBG_EN
|
| 341 |
|
|
|
| 342 |
|
|
// Instruction memory interface
|
| 343 |
|
|
.imem2core_req_ack_i (core_imem_req_ack),
|
| 344 |
|
|
.core2imem_req_o (core_imem_req ),
|
| 345 |
|
|
.core2imem_cmd_o (core_imem_cmd ),
|
| 346 |
|
|
.core2imem_addr_o (core_imem_addr ),
|
| 347 |
|
|
.imem2core_rdata_i (core_imem_rdata ),
|
| 348 |
|
|
.imem2core_resp_i (core_imem_resp ),
|
| 349 |
|
|
|
| 350 |
|
|
// Data memory interface
|
| 351 |
|
|
.dmem2core_req_ack_i (core_dmem_req_ack),
|
| 352 |
|
|
.core2dmem_req_o (core_dmem_req ),
|
| 353 |
|
|
.core2dmem_cmd_o (core_dmem_cmd ),
|
| 354 |
|
|
.core2dmem_width_o (core_dmem_width ),
|
| 355 |
|
|
.core2dmem_addr_o (core_dmem_addr ),
|
| 356 |
|
|
.core2dmem_wdata_o (core_dmem_wdata ),
|
| 357 |
|
|
.dmem2core_rdata_i (core_dmem_rdata ),
|
| 358 |
|
|
.dmem2core_resp_i (core_dmem_resp )
|
| 359 |
|
|
);
|
| 360 |
|
|
|
| 361 |
|
|
|
| 362 |
|
|
`ifdef SCR1_TCM_EN
|
| 363 |
|
|
//-------------------------------------------------------------------------------
|
| 364 |
|
|
// TCM instance
|
| 365 |
|
|
//-------------------------------------------------------------------------------
|
| 366 |
|
|
scr1_tcm #(
|
| 367 |
|
|
.SCR1_TCM_SIZE (`SCR1_DMEM_AWIDTH'(~SCR1_TCM_ADDR_MASK + 1'b1))
|
| 368 |
|
|
) i_tcm (
|
| 369 |
|
|
.clk (clk ),
|
| 370 |
|
|
.rst_n (core_rst_n_local),
|
| 371 |
|
|
|
| 372 |
|
|
// Instruction interface to TCM
|
| 373 |
|
|
.imem_req_ack (tcm_imem_req_ack),
|
| 374 |
|
|
.imem_req (tcm_imem_req ),
|
| 375 |
|
|
.imem_addr (tcm_imem_addr ),
|
| 376 |
|
|
.imem_rdata (tcm_imem_rdata ),
|
| 377 |
|
|
.imem_resp (tcm_imem_resp ),
|
| 378 |
|
|
|
| 379 |
|
|
// Data interface to TCM
|
| 380 |
|
|
.dmem_req_ack (tcm_dmem_req_ack),
|
| 381 |
|
|
.dmem_req (tcm_dmem_req ),
|
| 382 |
|
|
.dmem_cmd (tcm_dmem_cmd ),
|
| 383 |
|
|
.dmem_width (tcm_dmem_width ),
|
| 384 |
|
|
.dmem_addr (tcm_dmem_addr ),
|
| 385 |
|
|
.dmem_wdata (tcm_dmem_wdata ),
|
| 386 |
|
|
.dmem_rdata (tcm_dmem_rdata ),
|
| 387 |
|
|
.dmem_resp (tcm_dmem_resp )
|
| 388 |
|
|
);
|
| 389 |
|
|
`endif // SCR1_TCM_EN
|
| 390 |
|
|
|
| 391 |
|
|
|
| 392 |
|
|
//-------------------------------------------------------------------------------
|
| 393 |
|
|
// Memory-mapped timer instance
|
| 394 |
|
|
//-------------------------------------------------------------------------------
|
| 395 |
|
|
scr1_timer i_timer (
|
| 396 |
|
|
// Common
|
| 397 |
|
|
.rst_n (core_rst_n_local ),
|
| 398 |
|
|
.clk (clk ),
|
| 399 |
|
|
.rtc_clk (rtc_clk ),
|
| 400 |
|
|
|
| 401 |
|
|
// Memory interface
|
| 402 |
|
|
.dmem_req (timer_dmem_req ),
|
| 403 |
|
|
.dmem_cmd (timer_dmem_cmd ),
|
| 404 |
|
|
.dmem_width (timer_dmem_width ),
|
| 405 |
|
|
.dmem_addr (timer_dmem_addr ),
|
| 406 |
|
|
.dmem_wdata (timer_dmem_wdata ),
|
| 407 |
|
|
.dmem_req_ack (timer_dmem_req_ack),
|
| 408 |
|
|
.dmem_rdata (timer_dmem_rdata ),
|
| 409 |
|
|
.dmem_resp (timer_dmem_resp ),
|
| 410 |
|
|
|
| 411 |
|
|
// Timer interface
|
| 412 |
|
|
.timer_val (timer_val ),
|
| 413 |
|
|
.timer_irq (timer_irq )
|
| 414 |
|
|
);
|
| 415 |
|
|
|
| 416 |
|
|
|
| 417 |
|
|
`ifdef SCR1_IMEM_ROUTER_EN
|
| 418 |
|
|
//-------------------------------------------------------------------------------
|
| 419 |
|
|
// Instruction memory router
|
| 420 |
|
|
//-------------------------------------------------------------------------------
|
| 421 |
|
|
scr1_imem_router #(
|
| 422 |
|
|
.SCR1_ADDR_MASK (SCR1_TCM_ADDR_MASK),
|
| 423 |
|
|
.SCR1_ADDR_PATTERN (SCR1_TCM_ADDR_PATTERN)
|
| 424 |
|
|
) i_imem_router (
|
| 425 |
|
|
.rst_n (core_rst_n_local ),
|
| 426 |
|
|
.clk (clk ),
|
| 427 |
|
|
|
| 428 |
|
|
// Interface to core
|
| 429 |
|
|
.imem_req_ack (core_imem_req_ack),
|
| 430 |
|
|
.imem_req (core_imem_req ),
|
| 431 |
|
|
.imem_cmd (core_imem_cmd ),
|
| 432 |
|
|
.imem_addr (core_imem_addr ),
|
| 433 |
|
|
.imem_rdata (core_imem_rdata ),
|
| 434 |
|
|
.imem_resp (core_imem_resp ),
|
| 435 |
|
|
|
| 436 |
|
|
// Interface to AXI bridge
|
| 437 |
|
|
.port0_req_ack (axi_imem_req_ack ),
|
| 438 |
|
|
.port0_req (axi_imem_req ),
|
| 439 |
|
|
.port0_cmd (axi_imem_cmd ),
|
| 440 |
|
|
.port0_addr (axi_imem_addr ),
|
| 441 |
|
|
.port0_rdata (axi_imem_rdata ),
|
| 442 |
|
|
.port0_resp (axi_imem_resp ),
|
| 443 |
|
|
|
| 444 |
|
|
// Interface to TCM
|
| 445 |
|
|
.port1_req_ack (tcm_imem_req_ack ),
|
| 446 |
|
|
.port1_req (tcm_imem_req ),
|
| 447 |
|
|
.port1_cmd (tcm_imem_cmd ),
|
| 448 |
|
|
.port1_addr (tcm_imem_addr ),
|
| 449 |
|
|
.port1_rdata (tcm_imem_rdata ),
|
| 450 |
|
|
.port1_resp (tcm_imem_resp )
|
| 451 |
|
|
);
|
| 452 |
|
|
|
| 453 |
|
|
`else // SCR1_IMEM_ROUTER_EN
|
| 454 |
|
|
|
| 455 |
|
|
assign axi_imem_req = core_imem_req;
|
| 456 |
|
|
assign axi_imem_cmd = core_imem_cmd;
|
| 457 |
|
|
assign axi_imem_addr = core_imem_addr;
|
| 458 |
|
|
assign core_imem_req_ack = axi_imem_req_ack;
|
| 459 |
|
|
assign core_imem_resp = axi_imem_resp;
|
| 460 |
|
|
assign core_imem_rdata = axi_imem_rdata;
|
| 461 |
|
|
|
| 462 |
|
|
`endif // SCR1_IMEM_ROUTER_EN
|
| 463 |
|
|
|
| 464 |
|
|
|
| 465 |
|
|
//-------------------------------------------------------------------------------
|
| 466 |
|
|
// Data memory router
|
| 467 |
|
|
//-------------------------------------------------------------------------------
|
| 468 |
|
|
scr1_dmem_router #(
|
| 469 |
|
|
|
| 470 |
|
|
`ifdef SCR1_TCM_EN
|
| 471 |
|
|
.SCR1_PORT1_ADDR_MASK (SCR1_TCM_ADDR_MASK),
|
| 472 |
|
|
.SCR1_PORT1_ADDR_PATTERN (SCR1_TCM_ADDR_PATTERN),
|
| 473 |
|
|
`else // SCR1_TCM_EN
|
| 474 |
|
|
.SCR1_PORT1_ADDR_MASK (32'h00000000),
|
| 475 |
|
|
.SCR1_PORT1_ADDR_PATTERN (32'hFFFFFFFF),
|
| 476 |
|
|
`endif // SCR1_TCM_EN
|
| 477 |
|
|
|
| 478 |
|
|
.SCR1_PORT2_ADDR_MASK (SCR1_TIMER_ADDR_MASK),
|
| 479 |
|
|
.SCR1_PORT2_ADDR_PATTERN (SCR1_TIMER_ADDR_PATTERN)
|
| 480 |
|
|
|
| 481 |
|
|
) i_dmem_router (
|
| 482 |
|
|
.rst_n (core_rst_n_local ),
|
| 483 |
|
|
.clk (clk ),
|
| 484 |
|
|
|
| 485 |
|
|
// Interface to core
|
| 486 |
|
|
.dmem_req_ack (core_dmem_req_ack ),
|
| 487 |
|
|
.dmem_req (core_dmem_req ),
|
| 488 |
|
|
.dmem_cmd (core_dmem_cmd ),
|
| 489 |
|
|
.dmem_width (core_dmem_width ),
|
| 490 |
|
|
.dmem_addr (core_dmem_addr ),
|
| 491 |
|
|
.dmem_wdata (core_dmem_wdata ),
|
| 492 |
|
|
.dmem_rdata (core_dmem_rdata ),
|
| 493 |
|
|
.dmem_resp (core_dmem_resp ),
|
| 494 |
|
|
|
| 495 |
|
|
`ifdef SCR1_TCM_EN
|
| 496 |
|
|
// Interface to TCM
|
| 497 |
|
|
.port1_req_ack (tcm_dmem_req_ack ),
|
| 498 |
|
|
.port1_req (tcm_dmem_req ),
|
| 499 |
|
|
.port1_cmd (tcm_dmem_cmd ),
|
| 500 |
|
|
.port1_width (tcm_dmem_width ),
|
| 501 |
|
|
.port1_addr (tcm_dmem_addr ),
|
| 502 |
|
|
.port1_wdata (tcm_dmem_wdata ),
|
| 503 |
|
|
.port1_rdata (tcm_dmem_rdata ),
|
| 504 |
|
|
.port1_resp (tcm_dmem_resp ),
|
| 505 |
|
|
`else // SCR1_TCM_EN
|
| 506 |
|
|
.port1_req_ack (1'b0 ),
|
| 507 |
|
|
.port1_req ( ),
|
| 508 |
|
|
.port1_cmd ( ),
|
| 509 |
|
|
.port1_width ( ),
|
| 510 |
|
|
.port1_addr ( ),
|
| 511 |
|
|
.port1_wdata ( ),
|
| 512 |
|
|
.port1_rdata ('0 ),
|
| 513 |
|
|
.port1_resp (SCR1_MEM_RESP_RDY_ER),
|
| 514 |
|
|
`endif // SCR1_TCM_EN
|
| 515 |
|
|
|
| 516 |
|
|
// Interface to memory-mapped timer
|
| 517 |
|
|
.port2_req_ack (timer_dmem_req_ack ),
|
| 518 |
|
|
.port2_req (timer_dmem_req ),
|
| 519 |
|
|
.port2_cmd (timer_dmem_cmd ),
|
| 520 |
|
|
.port2_width (timer_dmem_width ),
|
| 521 |
|
|
.port2_addr (timer_dmem_addr ),
|
| 522 |
|
|
.port2_wdata (timer_dmem_wdata ),
|
| 523 |
|
|
.port2_rdata (timer_dmem_rdata ),
|
| 524 |
|
|
.port2_resp (timer_dmem_resp ),
|
| 525 |
|
|
|
| 526 |
|
|
// Interface to AXI bridge
|
| 527 |
|
|
.port0_req_ack (axi_dmem_req_ack ),
|
| 528 |
|
|
.port0_req (axi_dmem_req ),
|
| 529 |
|
|
.port0_cmd (axi_dmem_cmd ),
|
| 530 |
|
|
.port0_width (axi_dmem_width ),
|
| 531 |
|
|
.port0_addr (axi_dmem_addr ),
|
| 532 |
|
|
.port0_wdata (axi_dmem_wdata ),
|
| 533 |
|
|
.port0_rdata (axi_dmem_rdata ),
|
| 534 |
|
|
.port0_resp (axi_dmem_resp )
|
| 535 |
|
|
);
|
| 536 |
|
|
|
| 537 |
|
|
|
| 538 |
|
|
//-------------------------------------------------------------------------------
|
| 539 |
|
|
// Instruction memory AXI bridge
|
| 540 |
|
|
//-------------------------------------------------------------------------------
|
| 541 |
|
|
scr1_mem_axi #(
|
| 542 |
|
|
`ifdef SCR1_IMEM_AXI_REQ_BP
|
| 543 |
|
|
.SCR1_AXI_REQ_BP (1),
|
| 544 |
|
|
`else // SCR1_IMEM_AXI_REQ_BP
|
| 545 |
|
|
.SCR1_AXI_REQ_BP (0),
|
| 546 |
|
|
`endif // SCR1_IMEM_AXI_REQ_BP
|
| 547 |
|
|
`ifdef SCR1_IMEM_AXI_RESP_BP
|
| 548 |
|
|
.SCR1_AXI_RESP_BP (1)
|
| 549 |
|
|
`else // SCR1_IMEM_AXI_RESP_BP
|
| 550 |
|
|
.SCR1_AXI_RESP_BP (0)
|
| 551 |
|
|
`endif // SCR1_IMEM_AXI_RESP_BP
|
| 552 |
|
|
) i_imem_axi (
|
| 553 |
|
|
.clk (clk ),
|
| 554 |
|
|
.rst_n (axi_rst_n ),
|
| 555 |
|
|
.axi_reinit (axi_reinit ),
|
| 556 |
|
|
|
| 557 |
|
|
// Interface to core
|
| 558 |
|
|
.core_idle (axi_imem_idle ),
|
| 559 |
|
|
.core_req_ack (axi_imem_req_ack ),
|
| 560 |
|
|
.core_req (axi_imem_req ),
|
| 561 |
|
|
.core_cmd (axi_imem_cmd ),
|
| 562 |
|
|
.core_width (SCR1_MEM_WIDTH_WORD ),
|
| 563 |
|
|
.core_addr (axi_imem_addr ),
|
| 564 |
|
|
.core_wdata ('0 ),
|
| 565 |
|
|
.core_rdata (axi_imem_rdata ),
|
| 566 |
|
|
.core_resp (axi_imem_resp ),
|
| 567 |
|
|
|
| 568 |
|
|
// AXI I/O
|
| 569 |
|
|
.awid (io_axi_imem_awid ),
|
| 570 |
|
|
.awaddr (io_axi_imem_awaddr ),
|
| 571 |
|
|
.awlen (io_axi_imem_awlen ),
|
| 572 |
|
|
.awsize (io_axi_imem_awsize ),
|
| 573 |
|
|
.awburst (io_axi_imem_awburst ),
|
| 574 |
|
|
.awlock (io_axi_imem_awlock ),
|
| 575 |
|
|
.awcache (io_axi_imem_awcache ),
|
| 576 |
|
|
.awprot (io_axi_imem_awprot ),
|
| 577 |
|
|
.awregion (io_axi_imem_awregion ),
|
| 578 |
|
|
.awuser (io_axi_imem_awuser ),
|
| 579 |
|
|
.awqos (io_axi_imem_awqos ),
|
| 580 |
|
|
.awvalid (io_axi_imem_awvalid ),
|
| 581 |
|
|
.awready (io_axi_imem_awready ),
|
| 582 |
|
|
.wdata (io_axi_imem_wdata ),
|
| 583 |
|
|
.wstrb (io_axi_imem_wstrb ),
|
| 584 |
|
|
.wlast (io_axi_imem_wlast ),
|
| 585 |
|
|
.wuser (io_axi_imem_wuser ),
|
| 586 |
|
|
.wvalid (io_axi_imem_wvalid ),
|
| 587 |
|
|
.wready (io_axi_imem_wready ),
|
| 588 |
|
|
.bid (io_axi_imem_bid ),
|
| 589 |
|
|
.bresp (io_axi_imem_bresp ),
|
| 590 |
|
|
.bvalid (io_axi_imem_bvalid ),
|
| 591 |
|
|
.buser (io_axi_imem_buser ),
|
| 592 |
|
|
.bready (io_axi_imem_bready ),
|
| 593 |
|
|
.arid (io_axi_imem_arid ),
|
| 594 |
|
|
.araddr (io_axi_imem_araddr ),
|
| 595 |
|
|
.arlen (io_axi_imem_arlen ),
|
| 596 |
|
|
.arsize (io_axi_imem_arsize ),
|
| 597 |
|
|
.arburst (io_axi_imem_arburst ),
|
| 598 |
|
|
.arlock (io_axi_imem_arlock ),
|
| 599 |
|
|
.arcache (io_axi_imem_arcache ),
|
| 600 |
|
|
.arprot (io_axi_imem_arprot ),
|
| 601 |
|
|
.arregion (io_axi_imem_arregion ),
|
| 602 |
|
|
.aruser (io_axi_imem_aruser ),
|
| 603 |
|
|
.arqos (io_axi_imem_arqos ),
|
| 604 |
|
|
.arvalid (io_axi_imem_arvalid ),
|
| 605 |
|
|
.arready (io_axi_imem_arready ),
|
| 606 |
|
|
.rid (io_axi_imem_rid ),
|
| 607 |
|
|
.rdata (io_axi_imem_rdata ),
|
| 608 |
|
|
.rresp (io_axi_imem_rresp ),
|
| 609 |
|
|
.rlast (io_axi_imem_rlast ),
|
| 610 |
|
|
.ruser (io_axi_imem_ruser ),
|
| 611 |
|
|
.rvalid (io_axi_imem_rvalid ),
|
| 612 |
|
|
.rready (io_axi_imem_rready )
|
| 613 |
|
|
);
|
| 614 |
|
|
|
| 615 |
|
|
|
| 616 |
|
|
//-------------------------------------------------------------------------------
|
| 617 |
|
|
// Data memory AXI bridge
|
| 618 |
|
|
//-------------------------------------------------------------------------------
|
| 619 |
|
|
scr1_mem_axi #(
|
| 620 |
|
|
`ifdef SCR1_DMEM_AXI_REQ_BP
|
| 621 |
|
|
.SCR1_AXI_REQ_BP (1),
|
| 622 |
|
|
`else // SCR1_DMEM_AXI_REQ_BP
|
| 623 |
|
|
.SCR1_AXI_REQ_BP (0),
|
| 624 |
|
|
`endif // SCR1_DMEM_AXI_REQ_BP
|
| 625 |
|
|
`ifdef SCR1_DMEM_AXI_RESP_BP
|
| 626 |
|
|
.SCR1_AXI_RESP_BP (1)
|
| 627 |
|
|
`else // SCR1_DMEM_AXI_RESP_BP
|
| 628 |
|
|
.SCR1_AXI_RESP_BP (0)
|
| 629 |
|
|
`endif // SCR1_DMEM_AXI_RESP_BP
|
| 630 |
|
|
) i_dmem_axi (
|
| 631 |
|
|
.clk (clk ),
|
| 632 |
|
|
.rst_n (axi_rst_n ),
|
| 633 |
|
|
.axi_reinit (axi_reinit ),
|
| 634 |
|
|
|
| 635 |
|
|
// Interface to core
|
| 636 |
|
|
.core_idle (axi_dmem_idle ),
|
| 637 |
|
|
.core_req_ack (axi_dmem_req_ack ),
|
| 638 |
|
|
.core_req (axi_dmem_req ),
|
| 639 |
|
|
.core_cmd (axi_dmem_cmd ),
|
| 640 |
|
|
.core_width (axi_dmem_width ),
|
| 641 |
|
|
.core_addr (axi_dmem_addr ),
|
| 642 |
|
|
.core_wdata (axi_dmem_wdata ),
|
| 643 |
|
|
.core_rdata (axi_dmem_rdata ),
|
| 644 |
|
|
.core_resp (axi_dmem_resp ),
|
| 645 |
|
|
|
| 646 |
|
|
// AXI I/O
|
| 647 |
|
|
.awid (io_axi_dmem_awid ),
|
| 648 |
|
|
.awaddr (io_axi_dmem_awaddr ),
|
| 649 |
|
|
.awlen (io_axi_dmem_awlen ),
|
| 650 |
|
|
.awsize (io_axi_dmem_awsize ),
|
| 651 |
|
|
.awburst (io_axi_dmem_awburst ),
|
| 652 |
|
|
.awlock (io_axi_dmem_awlock ),
|
| 653 |
|
|
.awcache (io_axi_dmem_awcache ),
|
| 654 |
|
|
.awprot (io_axi_dmem_awprot ),
|
| 655 |
|
|
.awregion (io_axi_dmem_awregion ),
|
| 656 |
|
|
.awuser (io_axi_dmem_awuser ),
|
| 657 |
|
|
.awqos (io_axi_dmem_awqos ),
|
| 658 |
|
|
.awvalid (io_axi_dmem_awvalid ),
|
| 659 |
|
|
.awready (io_axi_dmem_awready ),
|
| 660 |
|
|
.wdata (io_axi_dmem_wdata ),
|
| 661 |
|
|
.wstrb (io_axi_dmem_wstrb ),
|
| 662 |
|
|
.wlast (io_axi_dmem_wlast ),
|
| 663 |
|
|
.wuser (io_axi_dmem_wuser ),
|
| 664 |
|
|
.wvalid (io_axi_dmem_wvalid ),
|
| 665 |
|
|
.wready (io_axi_dmem_wready ),
|
| 666 |
|
|
.bid (io_axi_dmem_bid ),
|
| 667 |
|
|
.bresp (io_axi_dmem_bresp ),
|
| 668 |
|
|
.bvalid (io_axi_dmem_bvalid ),
|
| 669 |
|
|
.buser (io_axi_dmem_buser ),
|
| 670 |
|
|
.bready (io_axi_dmem_bready ),
|
| 671 |
|
|
.arid (io_axi_dmem_arid ),
|
| 672 |
|
|
.araddr (io_axi_dmem_araddr ),
|
| 673 |
|
|
.arlen (io_axi_dmem_arlen ),
|
| 674 |
|
|
.arsize (io_axi_dmem_arsize ),
|
| 675 |
|
|
.arburst (io_axi_dmem_arburst ),
|
| 676 |
|
|
.arlock (io_axi_dmem_arlock ),
|
| 677 |
|
|
.arcache (io_axi_dmem_arcache ),
|
| 678 |
|
|
.arprot (io_axi_dmem_arprot ),
|
| 679 |
|
|
.arregion (io_axi_dmem_arregion ),
|
| 680 |
|
|
.aruser (io_axi_dmem_aruser ),
|
| 681 |
|
|
.arqos (io_axi_dmem_arqos ),
|
| 682 |
|
|
.arvalid (io_axi_dmem_arvalid ),
|
| 683 |
|
|
.arready (io_axi_dmem_arready ),
|
| 684 |
|
|
.rid (io_axi_dmem_rid ),
|
| 685 |
|
|
.rdata (io_axi_dmem_rdata ),
|
| 686 |
|
|
.rresp (io_axi_dmem_rresp ),
|
| 687 |
|
|
.rlast (io_axi_dmem_rlast ),
|
| 688 |
|
|
.ruser (io_axi_dmem_ruser ),
|
| 689 |
|
|
.rvalid (io_axi_dmem_rvalid ),
|
| 690 |
|
|
.rready (io_axi_dmem_rready )
|
| 691 |
|
|
);
|
| 692 |
|
|
|
| 693 |
|
|
//-------------------------------------------------------------------------------
|
| 694 |
|
|
// AXI reinit logic
|
| 695 |
|
|
//-------------------------------------------------------------------------------
|
| 696 |
|
|
always_ff @(negedge core_rst_n_local, posedge clk) begin
|
| 697 |
|
|
if (~core_rst_n_local) axi_reinit <= 1'b1;
|
| 698 |
|
|
else if (axi_imem_idle & axi_dmem_idle) axi_reinit <= 1'b0;
|
| 699 |
|
|
end
|
| 700 |
|
|
|
| 701 |
|
|
endmodule : scr1_top_axi
|
