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dinesha |
# Copyright 2020 Efabless Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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# inputs expected as env vars
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#set opt $::env(SYNTH_OPT)
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########### config.tcl ##################
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# User config
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# User config
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set ::env(DESIGN_DIR) ../
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set ::env(PROJ_DIR) ../../../../
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# User config
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set ::env(DESIGN_NAME) scr1_top_wb
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# Change if needed
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set ::env(VERILOG_FILES) [glob \
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../src/core/pipeline/scr1_pipe_top.sv \
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../src/core/scr1_core_top.sv \
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../src/core/scr1_dm.sv \
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../src/core/scr1_tapc_synchronizer.sv \
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../src/core/scr1_clk_ctrl.sv \
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../src/core/scr1_scu.sv \
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../src/core/scr1_tapc.sv \
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../src/core/scr1_tapc_shift_reg.sv \
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../src/core/scr1_dmi.sv \
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../src/core/primitives/scr1_reset_cells.sv \
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../src/core/pipeline/scr1_pipe_ifu.sv \
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../src/core/pipeline/scr1_pipe_idu.sv \
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../src/core/pipeline/scr1_pipe_exu.sv \
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../src/core/pipeline/scr1_pipe_mprf.sv \
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../src/core/pipeline/scr1_pipe_csr.sv \
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../src/core/pipeline/scr1_pipe_ialu.sv \
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../src/core/pipeline/scr1_pipe_lsu.sv \
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../src/core/pipeline/scr1_pipe_hdu.sv \
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../src/core/pipeline/scr1_pipe_tdu.sv \
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../src/core/pipeline/scr1_ipic.sv \
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../src/top/scr1_dmem_router.sv \
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../src/top/scr1_imem_router.sv \
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../src/top/scr1_tcm.sv \
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../src/top/scr1_timer.sv \
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../src/top/scr1_top_wb.sv \
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../src/top/scr1_dmem_wb.sv \
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../src/top/scr1_imem_wb.sv \
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../../../lib/sync_fifo.sv ]
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#set ::env(VERILOG_FILES_BLACKBOX) [glob \
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# $::env(DESIGN_DIR)/src/top/scr1_dp_memory.sv ]
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set ::env(VERILOG_INCLUDE_DIRS) [glob $::env(DESIGN_DIR)/src/includes]
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set ::env(SYNTH_DEFINES) [list YOSYS ]
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#set ::env(SYNTH_DEFINES) [list SCR1_DBG_EN SCR1_MPRF_RAM ]
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set ::env(LIB_SYNTH) ./tmp/trimmed.lib
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#set ::env(SDC_FILE) "./designs/aes128/src/aes128.sdc"
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# Fill this
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set ::env(CLOCK_PERIOD) "10"
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set ::env(CLOCK_PORT) "clk"
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set ::env(CLOCK_TREE_SYNTH) 0
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set ::env(RUN_SIMPLE_CTS) 0
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set ::env(SYNTH_BUFFERING) 0
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set ::env(SYNTH_SIZING) 0
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set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hd__inv_8"
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set ::env(SYNTH_CAP_LOAD) "17.65"
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set ::env(SYNTH_MAX_TRAN) "[expr {0.1*10.0}]"
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set ::env(SYNTH_MAX_FANOUT) 6
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set ::env(FP_CORE_UTIL) 50
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set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
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set ::env(CELL_PAD) 4
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set ::env(SYNTH_NO_FLAT) "0"
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set ::env(SYNTH_STRATEGY) "AREA 0"
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set ::env(SYNTH_TIELO_PORT) "sky130_fd_sc_hd__conb_1 LO"
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set ::env(SYNTH_TIEHI_PORT) "sky130_fd_sc_hd__conb_1 HI"
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set ::env(SYNTH_MIN_BUF_PORT) "sky130_fd_sc_hd__buf_2 A X"
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set ::env(CLOCK_NET) $::env(CLOCK_PORT)
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set ::env(yosys_tmp_file_tag) "./tmp/"
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set ::env(TMP_DIR) "./tmp/"
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set ::env(yosys_netlist_dir) "./netlist"
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set ::env(yosys_report_file_tag) "./reports/yosys"
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set ::env(yosys_result_file_tag) "./reports/yosys.synthesis"
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set ::env(SAVE_NETLIST) $::env(yosys_netlist_dir)/$::env(DESIGN_NAME).gv
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########### End of config.tcl
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set buffering $::env(SYNTH_BUFFERING)
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set sizing $::env(SYNTH_SIZING)
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yosys -import
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set vtop $::env(DESIGN_NAME)
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#set sdc_file $::env(SDC_FILE)
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set sclib $::env(LIB_SYNTH)
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if { [info exists ::env(SYNTH_DEFINES) ] } {
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foreach define $::env(SYNTH_DEFINES) {
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log "Defining $define"
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verilog_defines -D$define
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}
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}
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set vIdirsArgs ""
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if {[info exist ::env(VERILOG_INCLUDE_DIRS)]} {
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foreach dir $::env(VERILOG_INCLUDE_DIRS) {
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log "Adding include file -I$dir "
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lappend vIdirsArgs "-I$dir"
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}
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set vIdirsArgs [join $vIdirsArgs]
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}
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if { [info exists ::env(EXTRA_LIBS) ] } {
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foreach lib $::env(EXTRA_LIBS) {
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read_liberty {*}$vIdirsArgs -lib -ignore_miss_dir -setattr blackbox $lib
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}
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}
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# ns expected (in sdc as well)
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set clock_period [expr {$::env(CLOCK_PERIOD)*1000}]
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set driver $::env(SYNTH_DRIVING_CELL)
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set cload $::env(SYNTH_CAP_LOAD)
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# input pin cap of IN_3VX8
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set max_FO $::env(SYNTH_MAX_FANOUT)
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if {![info exist ::env(SYNTH_MAX_TRAN)]} {
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set ::env(SYNTH_MAX_TRAN) [expr {0.1*$clock_period}]
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} else {
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set ::env(SYNTH_MAX_TRAN) [expr {$::env(SYNTH_MAX_TRAN) * 1000}]
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}
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set max_Tran $::env(SYNTH_MAX_TRAN)
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# Mapping parameters
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set A_factor 0.00
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set B_factor 0.88
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set F_factor 0.00
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# Don't change these unless you know what you are doing
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set stat_ext ".stat.rpt"
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set chk_ext ".chk.rpt"
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set gl_ext ".gl.v"
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set constr_ext ".$clock_period.constr"
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set timing_ext ".timing.txt"
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set abc_ext ".abc"
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# get old sdc, add library specific stuff for abc scripts
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set sdc_file $::env(yosys_tmp_file_tag).sdc
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set outfile [open ${sdc_file} w]
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#puts $outfile $sdc_data
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puts $outfile "set_driving_cell ${driver}"
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puts $outfile "set_load ${cload}"
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close $outfile
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# ABC Scrips
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set abc_rs_K "resub,-K,"
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set abc_rs "resub"
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set abc_rsz "resub,-z"
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set abc_rw_K "rewrite,-K,"
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set abc_rw "rewrite"
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set abc_rwz "rewrite,-z"
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set abc_rf "refactor"
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set abc_rfz "refactor,-z"
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set abc_b "balance"
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set abc_resyn2 "${abc_b}; ${abc_rw}; ${abc_rf}; ${abc_b}; ${abc_rw}; ${abc_rwz}; ${abc_b}; ${abc_rfz}; ${abc_rwz}; ${abc_b}"
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set abc_share "strash; multi,-m; ${abc_resyn2}"
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set abc_resyn2a "${abc_b};${abc_rw};${abc_b};${abc_rw};${abc_rwz};${abc_b};${abc_rwz};${abc_b}"
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set abc_resyn3 "balance;resub;resub,-K,6;balance;resub,-z;resub,-z,-K,6;balance;resub,-z,-K,5;balance"
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set abc_resyn2rs "${abc_b};${abc_rs_K},6;${abc_rw};${abc_rs_K},6,-N,2;${abc_rf};${abc_rs_K},8;${abc_rw};${abc_rs_K},10;${abc_rwz};${abc_rs_K},10,-N,2;${abc_b},${abc_rs_K},12;${abc_rfz};${abc_rs_K},12,-N,2;${abc_rwz};${abc_b}"
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set abc_choice "fraig_store; ${abc_resyn2}; fraig_store; ${abc_resyn2}; fraig_store; fraig_restore"
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set abc_choice2 "fraig_store; balance; fraig_store; ${abc_resyn2}; fraig_store; ${abc_resyn2}; fraig_store; ${abc_resyn2}; fraig_store; fraig_restore"
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set abc_map_old_cnt "map,-p,-a,-B,0.2,-A,0.9,-M,0"
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set abc_map_old_dly "map,-p,-B,0.2,-A,0.9,-M,0"
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set abc_retime_area "retime,-D,{D},-M,5"
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set abc_retime_dly "retime,-D,{D},-M,6"
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set abc_map_new_area "amap,-m,-Q,0.1,-F,20,-A,20,-C,5000"
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set abc_area_recovery_1 "${abc_choice}; map;"
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set abc_area_recovery_2 "${abc_choice2}; map;"
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set map_old_cnt "map,-p,-a,-B,0.2,-A,0.9,-M,0"
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set map_old_dly "map,-p,-B,0.2,-A,0.9,-M,0"
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set abc_retime_area "retime,-D,{D},-M,5"
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set abc_retime_dly "retime,-D,{D},-M,6"
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set abc_map_new_area "amap,-m,-Q,0.1,-F,20,-A,20,-C,5000"
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if {$buffering==1} {
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set abc_fine_tune "buffer,-N,${max_FO},-S,${max_Tran};upsize,{D};dnsize,{D}"
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} elseif {$sizing} {
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set abc_fine_tune "upsize,{D};dnsize,{D}"
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} else {
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set abc_fine_tune ""
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}
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set delay_scripts [list \
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"+read_constr,${sdc_file};fx;mfs;strash;refactor;${abc_resyn2};${abc_retime_dly}; scleanup;${abc_map_old_dly};retime,-D,{D};${abc_fine_tune};stime,-p;print_stats -m" \
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\
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"+read_constr,${sdc_file};fx;mfs;strash;refactor;${abc_resyn2};${abc_retime_dly}; scleanup;${abc_choice2};${abc_map_old_dly};${abc_area_recovery_2}; retime,-D,{D};${abc_fine_tune};stime,-p;print_stats -m" \
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\
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"+read_constr,${sdc_file};fx;mfs;strash;refactor;${abc_resyn2};${abc_retime_dly}; scleanup;${abc_choice};${abc_map_old_dly};${abc_area_recovery_1}; retime,-D,{D};${abc_fine_tune};stime,-p;print_stats -m" \
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\
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"+read_constr,${sdc_file};fx;mfs;strash;refactor;${abc_resyn2};${abc_retime_area};scleanup;${abc_choice2};${abc_map_new_area};${abc_choice2};${abc_map_old_dly};retime,-D,{D};${abc_fine_tune};stime,-p;print_stats -m" \
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]
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set area_scripts [list \
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"+read_constr,${sdc_file};fx;mfs;strash;refactor;${abc_resyn2};${abc_retime_area};scleanup;${abc_choice2};${abc_map_new_area};retime,-D,{D};${abc_fine_tune};stime,-p;print_stats -m" \
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\
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"+read_constr,${sdc_file};fx;mfs;strash;refactor;${abc_resyn2};${abc_retime_area};scleanup;${abc_choice2};${abc_map_new_area};${abc_choice2};${abc_map_new_area};retime,-D,{D};${abc_fine_tune};stime,-p;print_stats -m" \
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\
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"+read_constr,${sdc_file};fx;mfs;strash;refactor;${abc_choice2};${abc_retime_area};scleanup;${abc_choice2};${abc_map_new_area};${abc_choice2};${abc_map_new_area};retime,-D,{D};${abc_fine_tune};stime,-p;print_stats -m" \
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]
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set all_scripts [list {*}$delay_scripts {*}$area_scripts]
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set strategy_parts [split $::env(SYNTH_STRATEGY)]
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proc synth_strategy_format_err { } {
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upvar area_scripts area_scripts
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upvar delay_scripts delay_scripts
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log -stderr "\[ERROR] Misformatted SYNTH_STRATEGY (\"$::env(SYNTH_STRATEGY)\")."
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log -stderr "\[ERROR] Correct format is \"DELAY|AREA 0-[expr [llength $delay_scripts]-1]|0-[expr [llength $area_scripts]-1]\"."
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exit 1
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}
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if { [llength $strategy_parts] != 2 } {
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synth_strategy_format_err
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}
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set strategy_type [lindex $strategy_parts 0]
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set strategy_type_idx [lindex $strategy_parts 1]
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if { $strategy_type != "AREA" && $strategy_type != "DELAY" } {
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log -stderr "\[ERROR] AREA|DELAY tokens not found. ($strategy_type)"
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synth_strategy_format_err
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}
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if { $strategy_type == "DELAY" && $strategy_type_idx >= [llength $delay_scripts] } {
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log -stderr "\[ERROR] strategy index ($strategy_type_idx) is too high."
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synth_strategy_format_err
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}
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if { $strategy_type == "AREA" && $strategy_type_idx >= [llength $area_scripts] } {
|
| 280 |
|
|
log -stderr "\[ERROR] strategy index ($strategy_type_idx) is too high."
|
| 281 |
|
|
synth_strategy_format_err
|
| 282 |
|
|
}
|
| 283 |
|
|
|
| 284 |
|
|
if { $strategy_type == "DELAY" } {
|
| 285 |
|
|
set strategy $strategy_type_idx
|
| 286 |
|
|
} else {
|
| 287 |
|
|
set strategy [expr {[llength $delay_scripts]+$strategy_type_idx}]
|
| 288 |
|
|
}
|
| 289 |
|
|
|
| 290 |
|
|
|
| 291 |
|
|
for { set i 0 } { $i < [llength $::env(VERILOG_FILES)] } { incr i } {
|
| 292 |
|
|
read_verilog -sv {*}$vIdirsArgs [lindex $::env(VERILOG_FILES) $i]
|
| 293 |
|
|
}
|
| 294 |
|
|
|
| 295 |
|
|
if { [info exists ::env(VERILOG_FILES_BLACKBOX)] } {
|
| 296 |
|
|
foreach verilog_file $::env(VERILOG_FILES_BLACKBOX) {
|
| 297 |
|
|
read_verilog -sv {*}$vIdirsArgs -lib $verilog_file
|
| 298 |
|
|
}
|
| 299 |
|
|
}
|
| 300 |
|
|
select -module $vtop
|
| 301 |
|
|
show -format dot -prefix $::env(TMP_DIR)/synthesis/hierarchy
|
| 302 |
|
|
select -clear
|
| 303 |
|
|
|
| 304 |
|
|
hierarchy -check -top $vtop
|
| 305 |
|
|
|
| 306 |
|
|
# Infer tri-state buffers.
|
| 307 |
|
|
set tbuf_map false
|
| 308 |
|
|
if { [info exists ::env(TRISTATE_BUFFER_MAP)] } {
|
| 309 |
|
|
if { [file exists $::env(TRISTATE_BUFFER_MAP)] } {
|
| 310 |
|
|
set tbuf_map true
|
| 311 |
|
|
tribuf
|
| 312 |
|
|
} else {
|
| 313 |
|
|
log "WARNING: TRISTATE_BUFFER_MAP is defined but could not be found: $::env(TRISTATE_BUFFER_MAP)"
|
| 314 |
|
|
}
|
| 315 |
|
|
}
|
| 316 |
|
|
|
| 317 |
|
|
if { $::env(SYNTH_NO_FLAT) } {
|
| 318 |
|
|
synth -top $vtop
|
| 319 |
|
|
} else {
|
| 320 |
|
|
synth -top $vtop -flatten
|
| 321 |
|
|
}
|
| 322 |
|
|
|
| 323 |
|
|
share -aggressive
|
| 324 |
|
|
opt
|
| 325 |
|
|
opt_clean -purge
|
| 326 |
|
|
|
| 327 |
|
|
tee -o "$::env(yosys_report_file_tag)_pre.stat" stat
|
| 328 |
|
|
|
| 329 |
|
|
# Map tri-state buffers.
|
| 330 |
|
|
if { $tbuf_map } {
|
| 331 |
|
|
log {mapping tbuf}
|
| 332 |
|
|
techmap -map $::env(TRISTATE_BUFFER_MAP)
|
| 333 |
|
|
simplemap
|
| 334 |
|
|
}
|
| 335 |
|
|
|
| 336 |
|
|
# handle technology mapping of 4-MUX, and tell Yosys to infer 4-muxes
|
| 337 |
|
|
if { [info exists ::env(SYNTH_MUX4_MAP)] && [file exists $::env(SYNTH_MUX4_MAP)] } {
|
| 338 |
|
|
muxcover -mux4
|
| 339 |
|
|
techmap -map $::env(SYNTH_MUX4_MAP)
|
| 340 |
|
|
simplemap
|
| 341 |
|
|
}
|
| 342 |
|
|
|
| 343 |
|
|
# handle technology mapping of 2-MUX
|
| 344 |
|
|
if { [info exists ::env(SYNTH_MUX_MAP)] && [file exists $::env(SYNTH_MUX_MAP)] } {
|
| 345 |
|
|
techmap -map $::env(SYNTH_MUX_MAP)
|
| 346 |
|
|
simplemap
|
| 347 |
|
|
}
|
| 348 |
|
|
|
| 349 |
|
|
# handle technology mapping of latches
|
| 350 |
|
|
if { [info exists ::env(SYNTH_LATCH_MAP)] && [file exists $::env(SYNTH_LATCH_MAP)] } {
|
| 351 |
|
|
techmap -map $::env(SYNTH_LATCH_MAP)
|
| 352 |
|
|
simplemap
|
| 353 |
|
|
}
|
| 354 |
|
|
|
| 355 |
|
|
dfflibmap -liberty $sclib
|
| 356 |
|
|
tee -o "$::env(yosys_report_file_tag)_dff.stat" stat
|
| 357 |
|
|
|
| 358 |
|
|
if { [info exists ::env(SYNTH_EXPLORE)] && $::env(SYNTH_EXPLORE) } {
|
| 359 |
|
|
design -save myDesign
|
| 360 |
|
|
|
| 361 |
|
|
for { set index 0 } { $index < [llength $all_scripts] } { incr index } {
|
| 362 |
|
|
log "\[INFO\]: ABC: WireLoad : S_$index"
|
| 363 |
|
|
design -load myDesign
|
| 364 |
|
|
|
| 365 |
|
|
abc -D $clock_period \
|
| 366 |
|
|
-constr "$sdc_file" \
|
| 367 |
|
|
-liberty $sclib \
|
| 368 |
|
|
-script [lindex $all_scripts $index]
|
| 369 |
|
|
|
| 370 |
|
|
setundef -zero
|
| 371 |
|
|
|
| 372 |
|
|
hilomap -hicell {*}$::env(SYNTH_TIEHI_PORT) -locell {*}$::env(SYNTH_TIELO_PORT)
|
| 373 |
|
|
|
| 374 |
|
|
# get rid of the assignments that make verilog2def fail
|
| 375 |
|
|
splitnets
|
| 376 |
|
|
opt_clean -purge
|
| 377 |
|
|
insbuf -buf {*}$::env(SYNTH_MIN_BUF_PORT)
|
| 378 |
|
|
|
| 379 |
|
|
tee -o "$::env(yosys_report_file_tag)_$index$chk_ext" check
|
| 380 |
|
|
write_verilog -noattr -noexpr -nohex -nodec -defparam "$::env(yosys_result_file_tag)_$index.v"
|
| 381 |
|
|
design -reset
|
| 382 |
|
|
}
|
| 383 |
|
|
} else {
|
| 384 |
|
|
|
| 385 |
|
|
log "\[INFO\]: ABC: WireLoad : S_$strategy"
|
| 386 |
|
|
|
| 387 |
|
|
abc -D $clock_period \
|
| 388 |
|
|
-constr "$sdc_file" \
|
| 389 |
|
|
-liberty $sclib \
|
| 390 |
|
|
-script [lindex $all_scripts $strategy] \
|
| 391 |
|
|
-showtmp;
|
| 392 |
|
|
|
| 393 |
|
|
setundef -zero
|
| 394 |
|
|
|
| 395 |
|
|
hilomap -hicell {*}$::env(SYNTH_TIEHI_PORT) -locell {*}$::env(SYNTH_TIELO_PORT)
|
| 396 |
|
|
|
| 397 |
|
|
# get rid of the assignments that make verilog2def fail
|
| 398 |
|
|
splitnets
|
| 399 |
|
|
opt_clean -purge
|
| 400 |
|
|
insbuf -buf {*}$::env(SYNTH_MIN_BUF_PORT)
|
| 401 |
|
|
|
| 402 |
|
|
tee -o "$::env(yosys_report_file_tag)_$strategy$chk_ext" check
|
| 403 |
|
|
write_verilog -noattr -noexpr -nohex -nodec -defparam "$::env(SAVE_NETLIST)"
|
| 404 |
|
|
}
|
| 405 |
|
|
|
| 406 |
|
|
if { $::env(SYNTH_NO_FLAT) } {
|
| 407 |
|
|
design -reset
|
| 408 |
|
|
file copy -force $::env(SAVE_NETLIST) $::env(yosys_tmp_file_tag)_unflat.v
|
| 409 |
|
|
read_verilog -sv $::env(SAVE_NETLIST)
|
| 410 |
|
|
synth -top $vtop -flatten
|
| 411 |
|
|
splitnets
|
| 412 |
|
|
opt_clean -purge
|
| 413 |
|
|
insbuf -buf {*}$::env(SYNTH_MIN_BUF_PORT)
|
| 414 |
|
|
write_verilog -noattr -noexpr -nohex -nodec -defparam "$::env(SAVE_NETLIST)"
|
| 415 |
|
|
tee -o "$::env(yosys_report_file_tag)_$strategy$chk_ext" check
|
| 416 |
|
|
}
|
