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dinesha |
//////////////////////////////////////////////////////////////////////
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//// ////
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//// Wishbone Interconnect ////
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//// ////
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//// This file is part of the YIFive cores project ////
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//// http://www.opencores.org/cores/yifive/ ////
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//// ////
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//// Description ////
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//// 1. 3 masters and 3 slaves share bus Wishbone connection ////
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//// 2. This block implement simple round robine request ////
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//// ////
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//// To Do: ////
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//// nothing ////
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//// ////
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//// Author(s): ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// ////
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//// Revision : ////
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//// 0.1 - 12th June 2021, Dinesh A ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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module wb_interconnect(
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input logic clk_i,
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input logic rst_n,
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// Master 0 Interface
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input logic [31:0] m0_wbd_dat_i,
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input logic [31:0] m0_wbd_adr_i,
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input logic [3:0] m0_wbd_sel_i,
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input logic m0_wbd_we_i,
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input logic m0_wbd_cyc_i,
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input logic m0_wbd_stb_i,
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input logic [3:0] m0_wbd_tid_i, // target id
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output logic [31:0] m0_wbd_dat_o,
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output logic m0_wbd_ack_o,
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output logic m0_wbd_err_o,
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// Master 1 Interface
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input logic [31:0] m1_wbd_dat_i,
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input logic [31:0] m1_wbd_adr_i,
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input logic [3:0] m1_wbd_sel_i,
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input logic m1_wbd_we_i,
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input logic m1_wbd_cyc_i,
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input logic m1_wbd_stb_i,
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input logic [3:0] m1_wbd_tid_i, // target id
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output logic [31:0] m1_wbd_dat_o,
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output logic m1_wbd_ack_o,
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output logic m1_wbd_err_o,
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// Master 2 Interface
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input logic [31:0] m2_wbd_dat_i,
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input logic [31:0] m2_wbd_adr_i,
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input logic [3:0] m2_wbd_sel_i,
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input logic m2_wbd_we_i,
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input logic m2_wbd_cyc_i,
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input logic m2_wbd_stb_i,
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input logic [3:0] m2_wbd_tid_i, // target id
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output logic [31:0] m2_wbd_dat_o,
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output logic m2_wbd_ack_o,
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output logic m2_wbd_err_o,
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// Slave 0 Interface
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input logic [31:0] s0_wbd_dat_i,
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input logic s0_wbd_ack_i,
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input logic s0_wbd_err_i,
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output logic [31:0] s0_wbd_dat_o,
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output logic [31:0] s0_wbd_adr_o,
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output logic [3:0] s0_wbd_sel_o,
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output logic s0_wbd_we_o,
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output logic s0_wbd_cyc_o,
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output logic s0_wbd_stb_o,
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// Slave 1 Interface
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input logic [31:0] s1_wbd_dat_i,
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input logic s1_wbd_ack_i,
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input logic s1_wbd_err_i,
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output logic [31:0] s1_wbd_dat_o,
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output logic [31:0] s1_wbd_adr_o,
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output logic [3:0] s1_wbd_sel_o,
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output logic s1_wbd_we_o,
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output logic s1_wbd_cyc_o,
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output logic s1_wbd_stb_o,
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// Slave 2 Interface
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input logic [31:0] s2_wbd_dat_i,
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input logic s2_wbd_ack_i,
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input logic s2_wbd_err_i,
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output logic [31:0] s2_wbd_dat_o,
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output logic [31:0] s2_wbd_adr_o,
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output logic [3:0] s2_wbd_sel_o,
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output logic s2_wbd_we_o,
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output logic s2_wbd_cyc_o,
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output logic s2_wbd_stb_o
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);
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////////////////////////////////////////////////////////////////////
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//
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// Type define
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//
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// WishBone Wr Interface
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typedef struct packed {
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logic [31:0] wbd_dat;
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logic [31:0] wbd_adr;
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logic [3:0] wbd_sel;
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logic wbd_we;
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logic wbd_cyc;
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logic wbd_stb;
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logic [3:0] wbd_tid; // target id
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} type_wb_wr_intf;
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// WishBone Rd Interface
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typedef struct packed {
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logic [31:0] wbd_dat;
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logic wbd_ack;
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logic wbd_err;
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} type_wb_rd_intf;
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// Master Write Interface
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type_wb_wr_intf m0_wb_wr;
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type_wb_wr_intf m1_wb_wr;
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type_wb_wr_intf m2_wb_wr;
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// Master Read Interface
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type_wb_rd_intf m0_wb_rd;
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type_wb_rd_intf m1_wb_rd;
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type_wb_rd_intf m2_wb_rd;
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// Slave Write Interface
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type_wb_wr_intf s0_wb_wr;
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type_wb_wr_intf s1_wb_wr;
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type_wb_wr_intf s2_wb_wr;
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// Slave Read Interface
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type_wb_rd_intf s0_wb_rd;
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type_wb_rd_intf s1_wb_rd;
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type_wb_rd_intf s2_wb_rd;
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type_wb_wr_intf i_bus_m; // Multiplexed Master I/F
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type_wb_rd_intf i_bus_s; // Multiplexed Slave I/F
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//----------------------------------------
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// Master Mapping
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// -------------------------------------
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assign m0_wb_wr.wbd_dat = m0_wbd_dat_i;
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assign m0_wb_wr.wbd_adr = m0_wbd_adr_i;
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assign m0_wb_wr.wbd_sel = m0_wbd_sel_i;
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assign m0_wb_wr.wbd_we = m0_wbd_we_i;
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assign m0_wb_wr.wbd_cyc = m0_wbd_cyc_i;
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assign m0_wb_wr.wbd_stb = m0_wbd_stb_i;
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assign m0_wb_wr.wbd_tid = m0_wbd_tid_i;
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assign m1_wb_wr.wbd_dat = m1_wbd_dat_i;
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assign m1_wb_wr.wbd_adr = m1_wbd_adr_i;
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assign m1_wb_wr.wbd_sel = m1_wbd_sel_i;
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assign m1_wb_wr.wbd_we = m1_wbd_we_i;
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assign m1_wb_wr.wbd_cyc = m1_wbd_cyc_i;
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assign m1_wb_wr.wbd_stb = m1_wbd_stb_i;
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assign m1_wb_wr.wbd_tid = m1_wbd_tid_i;
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assign m2_wb_wr.wbd_dat = m2_wbd_dat_i;
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assign m2_wb_wr.wbd_adr = m2_wbd_adr_i;
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assign m2_wb_wr.wbd_sel = m2_wbd_sel_i;
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assign m2_wb_wr.wbd_we = m2_wbd_we_i;
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assign m2_wb_wr.wbd_cyc = m2_wbd_cyc_i;
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assign m2_wb_wr.wbd_stb = m2_wbd_stb_i;
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assign m2_wb_wr.wbd_tid = m2_wbd_tid_i;
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assign m0_wbd_dat_o = m0_wb_rd.wbd_dat;
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assign m0_wbd_ack_o = m0_wb_rd.wbd_ack;
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assign m0_wbd_err_o = m0_wb_rd.wbd_err;
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assign m1_wbd_dat_o = m1_wb_rd.wbd_dat;
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assign m1_wbd_ack_o = m1_wb_rd.wbd_ack;
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assign m1_wbd_err_o = m1_wb_rd.wbd_err;
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assign m2_wbd_dat_o = m2_wb_rd.wbd_dat;
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assign m2_wbd_ack_o = m2_wb_rd.wbd_ack;
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assign m2_wbd_err_o = m2_wb_rd.wbd_err;
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assign s0_wb_rd.wbd_dat = s0_wbd_dat_i ;
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assign s0_wb_rd.wbd_ack = s0_wbd_ack_i ;
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assign s0_wb_rd.wbd_err = s0_wbd_err_i ;
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assign s1_wb_rd.wbd_dat = s1_wbd_dat_i ;
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assign s1_wb_rd.wbd_ack = s1_wbd_ack_i ;
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assign s1_wb_rd.wbd_err = s1_wbd_err_i ;
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assign s2_wb_rd.wbd_dat = s2_wbd_dat_i ;
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assign s2_wb_rd.wbd_ack = s2_wbd_ack_i ;
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assign s2_wb_rd.wbd_err = s2_wbd_err_i ;
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//----------------------------------------
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// Slave Mapping
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// -------------------------------------
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assign s0_wbd_dat_o = s0_wb_wr.wbd_dat ;
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assign s0_wbd_adr_o = s0_wb_wr.wbd_adr ;
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assign s0_wbd_sel_o = s0_wb_wr.wbd_sel ;
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assign s0_wbd_we_o = s0_wb_wr.wbd_we ;
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assign s0_wbd_cyc_o = s0_wb_wr.wbd_cyc ;
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assign s0_wbd_stb_o = s0_wb_wr.wbd_stb ;
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assign s1_wbd_dat_o = s1_wb_wr.wbd_dat ;
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assign s1_wbd_adr_o = s1_wb_wr.wbd_adr ;
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assign s1_wbd_sel_o = s1_wb_wr.wbd_sel ;
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assign s1_wbd_we_o = s1_wb_wr.wbd_we ;
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assign s1_wbd_cyc_o = s1_wb_wr.wbd_cyc ;
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assign s1_wbd_stb_o = s1_wb_wr.wbd_stb ;
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assign s2_wbd_dat_o = s2_wb_wr.wbd_dat ;
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assign s2_wbd_adr_o = s2_wb_wr.wbd_adr ;
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assign s2_wbd_sel_o = s2_wb_wr.wbd_sel ;
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assign s2_wbd_we_o = s2_wb_wr.wbd_we ;
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assign s2_wbd_cyc_o = s2_wb_wr.wbd_cyc ;
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assign s2_wbd_stb_o = s2_wb_wr.wbd_stb ;
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//
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// arbitor
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//
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logic [1:0] gnt;
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wb_arb u_wb_arb(
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.clk(clk_i),
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.rstn(rst_n),
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.req({ m2_wbd_cyc_i,
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m1_wbd_cyc_i,
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m0_wbd_cyc_i}),
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.gnt(gnt)
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);
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// Generate Multiplexed Master Interface based on grant
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always_comb begin
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case(gnt)
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3'h0: i_bus_m = m0_wb_wr;
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3'h1: i_bus_m = m1_wb_wr;
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3'h2: i_bus_m = m2_wb_wr;
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default: i_bus_m = m0_wb_wr;
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endcase
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end
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// Generate Multiplexed Slave Interface based on target Id
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wire [3:0] wbd_tid = i_bus_m.wbd_tid; // to fix iverilog warning
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always_comb begin
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case(wbd_tid)
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3'h0: i_bus_s = s0_wb_rd;
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3'h1: i_bus_s = s1_wb_rd;
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3'h2: i_bus_s = s2_wb_rd;
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default: i_bus_s = s0_wb_rd;
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endcase
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end
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// Connect Master => Slave
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assign s0_wb_wr = (i_bus_m.wbd_tid == 2'b00) ? i_bus_m : 'h0;
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assign s1_wb_wr = (i_bus_m.wbd_tid == 2'b01) ? i_bus_m : 'h0;
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assign s2_wb_wr = (i_bus_m.wbd_tid == 2'b10) ? i_bus_m : 'h0;
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// Connect Slave to Master
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assign m0_wb_rd = (gnt == 2'b00) ? i_bus_s : 'h0;
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assign m1_wb_rd = (gnt == 2'b01) ? i_bus_s : 'h0;
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assign m2_wb_rd = (gnt == 2'b10) ? i_bus_s : 'h0;
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endmodule
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