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[/] [z80control/] [trunk/] [CII_Starter_USB_API_v1/] [HW/] [AUDIO_DAC.v] - Blame information for rev 12

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//Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors.  Please refer to the applicable
//agreement for further details.
 
module AUDIO_DAC (      //      Memory Side
                                        oFLASH_ADDR,iFLASH_DATA,
                                        oSDRAM_ADDR,iSDRAM_DATA,
                                        oSRAM_ADDR,iSRAM_DATA,
                                        //      Audio Side
                                        oAUD_BCK,
                                        oAUD_DATA,
                                        oAUD_LRCK,
                                        //      Control Signals
                                        iSrc_Select,
                                    iCLK_18_4,
                                        iRST_N  );
 
parameter       REF_CLK                 =       18432000;       //      18.432  MHz
parameter       SAMPLE_RATE             =       48000;          //      48              KHz
parameter       DATA_WIDTH              =       16;                     //      16              Bits
parameter       CHANNEL_NUM             =       2;                      //      Dual Channel
 
parameter       SIN_SAMPLE_DATA =       48;
parameter       FLASH_DATA_NUM  =       4194304;        //      4       MWords
parameter       SDRAM_DATA_NUM  =       4194304;        //      4       MWords
parameter       SRAM_DATA_NUM   =       262144;         //      256     KWords
 
parameter       FLASH_ADDR_WIDTH=       22;                     //      22      Address Line
parameter       SDRAM_ADDR_WIDTH=       22;                     //      22      Address Line
parameter       SRAM_ADDR_WIDTH=        18;                     //      18      Address Line
 
parameter       FLASH_DATA_WIDTH=       8;                      //      8       Bits
parameter       SDRAM_DATA_WIDTH=       16;                     //      16      Bits
parameter       SRAM_DATA_WIDTH=        16;                     //      16      Bits
 
////////////    Input Source Number     //////////////
parameter       SIN_SANPLE              =       0;
parameter       FLASH_DATA              =       1;
parameter       SDRAM_DATA              =       2;
parameter       SRAM_DATA               =       3;
//////////////////////////////////////////////////
//      Memory Side
output  [FLASH_ADDR_WIDTH-1:0]   oFLASH_ADDR;
input   [FLASH_DATA_WIDTH-1:0]   iFLASH_DATA;
output  [SDRAM_ADDR_WIDTH:0]     oSDRAM_ADDR;
input   [SDRAM_DATA_WIDTH-1:0]   iSDRAM_DATA;
output  [SRAM_ADDR_WIDTH:0]              oSRAM_ADDR;
input   [SRAM_DATA_WIDTH-1:0]    iSRAM_DATA;
//      Audio Side
output                  oAUD_DATA;
output                  oAUD_LRCK;
output  reg             oAUD_BCK;
//      Control Signals
input   [1:0]    iSrc_Select;
input                   iCLK_18_4;
input                   iRST_N;
//      Internal Registers and Wires
reg             [3:0]    BCK_DIV;
reg             [8:0]    LRCK_1X_DIV;
reg             [7:0]    LRCK_2X_DIV;
reg             [6:0]    LRCK_4X_DIV;
reg             [3:0]    SEL_Cont;
////////        DATA Counter    ////////
reg             [5:0]    SIN_Cont;
reg             [FLASH_ADDR_WIDTH-1:0]   FLASH_Cont;
reg             [SDRAM_ADDR_WIDTH-1:0]   SDRAM_Cont;
reg             [SRAM_ADDR_WIDTH-1:0]    SRAM_Cont;
////////////////////////////////////
reg             [DATA_WIDTH-1:0] Sin_Out;
reg             [DATA_WIDTH-1:0] FLASH_Out;
reg             [DATA_WIDTH-1:0] SDRAM_Out;
reg             [DATA_WIDTH-1:0] SRAM_Out;
reg             [DATA_WIDTH-1:0] FLASH_Out_Tmp;
reg             [DATA_WIDTH-1:0] SDRAM_Out_Tmp;
reg             [DATA_WIDTH-1:0] SRAM_Out_Tmp;
reg                                                     LRCK_1X;
reg                                                     LRCK_2X;
reg                                                     LRCK_4X;
 
////////////    AUD_BCK Generator       //////////////
always@(posedge iCLK_18_4 or negedge iRST_N)
begin
        if(!iRST_N)
        begin
                BCK_DIV         <=      0;
                oAUD_BCK        <=      0;
        end
        else
        begin
                if(BCK_DIV >= REF_CLK/(SAMPLE_RATE*DATA_WIDTH*CHANNEL_NUM*2)-1 )
                begin
                        BCK_DIV         <=      0;
                        oAUD_BCK        <=      ~oAUD_BCK;
                end
                else
                BCK_DIV         <=      BCK_DIV+1;
        end
end
//////////////////////////////////////////////////
////////////    AUD_LRCK Generator      //////////////
always@(posedge iCLK_18_4 or negedge iRST_N)
begin
        if(!iRST_N)
        begin
                LRCK_1X_DIV     <=      0;
                LRCK_2X_DIV     <=      0;
                LRCK_4X_DIV     <=      0;
                LRCK_1X         <=      0;
                LRCK_2X         <=      0;
                LRCK_4X         <=      0;
        end
        else
        begin
                //      LRCK 1X
                if(LRCK_1X_DIV >= REF_CLK/(SAMPLE_RATE*2)-1 )
                begin
                        LRCK_1X_DIV     <=      0;
                        LRCK_1X <=      ~LRCK_1X;
                end
                else
                LRCK_1X_DIV             <=      LRCK_1X_DIV+1;
                //      LRCK 2X
                if(LRCK_2X_DIV >= REF_CLK/(SAMPLE_RATE*4)-1 )
                begin
                        LRCK_2X_DIV     <=      0;
                        LRCK_2X <=      ~LRCK_2X;
                end
                else
                LRCK_2X_DIV             <=      LRCK_2X_DIV+1;
                //      LRCK 4X
                if(LRCK_4X_DIV >= REF_CLK/(SAMPLE_RATE*8)-1 )
                begin
                        LRCK_4X_DIV     <=      0;
                        LRCK_4X <=      ~LRCK_4X;
                end
                else
                LRCK_4X_DIV             <=      LRCK_4X_DIV+1;
        end
end
assign  oAUD_LRCK       =       LRCK_1X;
//////////////////////////////////////////////////
//////////      Sin LUT ADDR Generator  //////////////
always@(negedge LRCK_1X or negedge iRST_N)
begin
        if(!iRST_N)
        SIN_Cont        <=      0;
        else
        begin
                if(SIN_Cont < SIN_SAMPLE_DATA-1 )
                SIN_Cont        <=      SIN_Cont+1;
                else
                SIN_Cont        <=      0;
        end
end
//////////////////////////////////////////////////
//////////      FLASH ADDR Generator    //////////////
always@(negedge LRCK_4X or negedge iRST_N)
begin
        if(!iRST_N)
        FLASH_Cont      <=      0;
        else
        begin
                if(FLASH_Cont < FLASH_DATA_NUM-1 )
                FLASH_Cont      <=      FLASH_Cont+1;
                else
                FLASH_Cont      <=      0;
        end
end
assign  oFLASH_ADDR     =       FLASH_Cont;
//////////////////////////////////////////////////
//////////        FLASH DATA Reorder    //////////////
always@(posedge LRCK_4X or negedge iRST_N)
begin
        if(!iRST_N)
        FLASH_Out_Tmp   <=      0;
        else
        begin
                if(FLASH_Cont[0])
                FLASH_Out_Tmp[15:8]     <=      iFLASH_DATA;
                else
                FLASH_Out_Tmp[7:0]       <=      iFLASH_DATA;
        end
end
always@(negedge LRCK_2X or negedge iRST_N)
begin
        if(!iRST_N)
        FLASH_Out       <=      0;
        else
        FLASH_Out       <=      FLASH_Out_Tmp;
end
//////////////////////////////////////////////////
//////////      SDRAM ADDR Generator    //////////////
always@(negedge LRCK_2X or negedge iRST_N)
begin
        if(!iRST_N)
        SDRAM_Cont      <=      0;
        else
        begin
                if(SDRAM_Cont < SDRAM_DATA_NUM-1 )
                SDRAM_Cont      <=      SDRAM_Cont+1;
                else
                SDRAM_Cont      <=      0;
        end
end
assign  oSDRAM_ADDR     =       SDRAM_Cont;
//////////////////////////////////////////////////
//////////        SDRAM DATA Latch              //////////////
always@(posedge LRCK_2X or negedge iRST_N)
begin
        if(!iRST_N)
        SDRAM_Out_Tmp   <=      0;
        else
        SDRAM_Out_Tmp   <=      iSDRAM_DATA;
end
always@(negedge LRCK_2X or negedge iRST_N)
begin
        if(!iRST_N)
        SDRAM_Out       <=      0;
        else
        SDRAM_Out       <=      SDRAM_Out_Tmp;
end
//////////////////////////////////////////////////
////////////    SRAM ADDR Generator       ////////////
always@(negedge LRCK_2X or negedge iRST_N)
begin
        if(!iRST_N)
        SRAM_Cont       <=      0;
        else
        begin
                if(SRAM_Cont < SRAM_DATA_NUM-1 )
                SRAM_Cont       <=      SRAM_Cont+1;
                else
                SRAM_Cont       <=      0;
        end
end
assign  oSRAM_ADDR      =       SRAM_Cont;
//////////////////////////////////////////////////
//////////        SRAM DATA Latch               //////////////
always@(posedge LRCK_2X or negedge iRST_N)
begin
        if(!iRST_N)
        SRAM_Out_Tmp    <=      0;
        else
        SRAM_Out_Tmp    <=      iSRAM_DATA;
end
always@(negedge LRCK_2X or negedge iRST_N)
begin
        if(!iRST_N)
        SRAM_Out        <=      0;
        else
        SRAM_Out        <=      SRAM_Out_Tmp;
end
//////////////////////////////////////////////////
//////////      16 Bits PISO MSB First  //////////////
always@(negedge oAUD_BCK or negedge iRST_N)
begin
        if(!iRST_N)
        SEL_Cont        <=      0;
        else
        SEL_Cont        <=      SEL_Cont+1;
end
assign  oAUD_DATA       =       (iSrc_Select==SIN_SANPLE)       ?       Sin_Out[~SEL_Cont]      :
                                                (iSrc_Select==FLASH_DATA)       ?       FLASH_Out[~SEL_Cont]:
                                                (iSrc_Select==SDRAM_DATA)       ?       SDRAM_Out[~SEL_Cont]:
                                                                                                                SRAM_Out[~SEL_Cont]     ;
//////////////////////////////////////////////////
////////////    Sin Wave ROM Table      //////////////
always@(SIN_Cont)
begin
    case(SIN_Cont)
 
    1  :  Sin_Out       <=      4276    ;
    2  :  Sin_Out       <=      8480    ;
    3  :  Sin_Out       <=      12539   ;
    4  :  Sin_Out       <=      16383   ;
    5  :  Sin_Out       <=      19947   ;
    6  :  Sin_Out       <=      23169   ;
    7  :  Sin_Out       <=      25995   ;
    8  :  Sin_Out       <=      28377   ;
    9  :  Sin_Out       <=      30272   ;
    10  :  Sin_Out      <=      31650   ;
    11  :  Sin_Out      <=      32486   ;
    12  :  Sin_Out      <=      32767   ;
    13  :  Sin_Out      <=      32486   ;
    14  :  Sin_Out      <=      31650   ;
    15  :  Sin_Out      <=      30272   ;
    16  :  Sin_Out      <=      28377   ;
    17  :  Sin_Out      <=      25995   ;
    18  :  Sin_Out      <=      23169   ;
    19  :  Sin_Out      <=      19947   ;
    20  :  Sin_Out      <=      16383   ;
    21  :  Sin_Out      <=      12539   ;
    22  :  Sin_Out      <=      8480    ;
    23  :  Sin_Out      <=      4276    ;
    24  :  Sin_Out      <=      0       ;
    25  :  Sin_Out      <=      61259   ;
    26  :  Sin_Out      <=      57056   ;
    27  :  Sin_Out      <=      52997   ;
    28  :  Sin_Out      <=      49153   ;
    29  :  Sin_Out      <=      45589   ;
    30  :  Sin_Out      <=      42366   ;
    31  :  Sin_Out      <=      39540   ;
    32  :  Sin_Out      <=      37159   ;
    33  :  Sin_Out      <=      35263   ;
    34  :  Sin_Out      <=      33885   ;
    35  :  Sin_Out      <=      33049   ;
    36  :  Sin_Out      <=      32768   ;
    37  :  Sin_Out      <=      33049   ;
    38  :  Sin_Out      <=      33885   ;
    39  :  Sin_Out      <=      35263   ;
    40  :  Sin_Out      <=      37159   ;
    41  :  Sin_Out      <=      39540   ;
    42  :  Sin_Out      <=      42366   ;
    43  :  Sin_Out      <=      45589   ;
    44  :  Sin_Out      <=      49152   ;
    45  :  Sin_Out      <=      52997   ;
    46  :  Sin_Out      <=      57056   ;
    47  :  Sin_Out      <=      61259   ;
        default :
                   Sin_Out              <=              0                ;
        endcase
end
//////////////////////////////////////////////////
 
endmodule
 
 
 
 

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Subversion Repositories z80control

[/] [z80control/] [trunk/] [CII_Starter_USB_API_v1/] [HW/] [AUDIO_DAC.v] - Blame information for rev 12

Line No.	Rev	Author	Line
1	12	tylerapohl	`//Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your`
2			`//use of Altera Corporation's design tools, logic functions and other`
3			`//software and tools, and its AMPP partner logic functions, and any`
4			`//output files any of the foregoing (including device programming or`
5			`//simulation files), and any associated documentation or information are`
6			`//expressly subject to the terms and conditions of the Altera Program`
7			`//License Subscription Agreement or other applicable license agreement,`
8			`//including, without limitation, that your use is for the sole purpose`
9			`//of programming logic devices manufactured by Altera and sold by Altera`
10			`//or its authorized distributors. Please refer to the applicable`
11			`//agreement for further details.`
12
13			`module AUDIO_DAC ( // Memory Side`
14			`oFLASH_ADDR,iFLASH_DATA,`
15			`oSDRAM_ADDR,iSDRAM_DATA,`
16			`oSRAM_ADDR,iSRAM_DATA,`
17			`// Audio Side`
18			`oAUD_BCK,`
19			`oAUD_DATA,`
20			`oAUD_LRCK,`
21			`// Control Signals`
22			`iSrc_Select,`
23			`iCLK_18_4,`
24			`iRST_N );`
25
26			`parameter REF_CLK = 18432000; // 18.432 MHz`
27			`parameter SAMPLE_RATE = 48000; // 48 KHz`
28			`parameter DATA_WIDTH = 16; // 16 Bits`
29			`parameter CHANNEL_NUM = 2; // Dual Channel`
30
31			`parameter SIN_SAMPLE_DATA = 48;`
32			`parameter FLASH_DATA_NUM = 4194304; // 4 MWords`
33			`parameter SDRAM_DATA_NUM = 4194304; // 4 MWords`
34			`parameter SRAM_DATA_NUM = 262144; // 256 KWords`
35
36			`parameter FLASH_ADDR_WIDTH= 22; // 22 Address Line`
37			`parameter SDRAM_ADDR_WIDTH= 22; // 22 Address Line`
38			`parameter SRAM_ADDR_WIDTH= 18; // 18 Address Line`
39
40			`parameter FLASH_DATA_WIDTH= 8; // 8 Bits`
41			`parameter SDRAM_DATA_WIDTH= 16; // 16 Bits`
42			`parameter SRAM_DATA_WIDTH= 16; // 16 Bits`
43
44			`//////////// Input Source Number //////////////`
45			`parameter SIN_SANPLE = 0;`
46			`parameter FLASH_DATA = 1;`
47			`parameter SDRAM_DATA = 2;`
48			`parameter SRAM_DATA = 3;`
49			`//////////////////////////////////////////////////`
50			`// Memory Side`
51			`output [FLASH_ADDR_WIDTH-1:0] oFLASH_ADDR;`
52			`input [FLASH_DATA_WIDTH-1:0] iFLASH_DATA;`
53			`output [SDRAM_ADDR_WIDTH:0] oSDRAM_ADDR;`
54			`input [SDRAM_DATA_WIDTH-1:0] iSDRAM_DATA;`
55			`output [SRAM_ADDR_WIDTH:0] oSRAM_ADDR;`
56			`input [SRAM_DATA_WIDTH-1:0] iSRAM_DATA;`
57			`// Audio Side`
58			`output oAUD_DATA;`
59			`output oAUD_LRCK;`
60			`output reg oAUD_BCK;`
61			`// Control Signals`
62			`input [1:0] iSrc_Select;`
63			`input iCLK_18_4;`
64			`input iRST_N;`
65			`// Internal Registers and Wires`
66			`reg [3:0] BCK_DIV;`
67			`reg [8:0] LRCK_1X_DIV;`
68			`reg [7:0] LRCK_2X_DIV;`
69			`reg [6:0] LRCK_4X_DIV;`
70			`reg [3:0] SEL_Cont;`
71			`//////// DATA Counter ////////`
72			`reg [5:0] SIN_Cont;`
73			`reg [FLASH_ADDR_WIDTH-1:0] FLASH_Cont;`
74			`reg [SDRAM_ADDR_WIDTH-1:0] SDRAM_Cont;`
75			`reg [SRAM_ADDR_WIDTH-1:0] SRAM_Cont;`
76			`////////////////////////////////////`
77			`reg [DATA_WIDTH-1:0] Sin_Out;`
78			`reg [DATA_WIDTH-1:0] FLASH_Out;`
79			`reg [DATA_WIDTH-1:0] SDRAM_Out;`
80			`reg [DATA_WIDTH-1:0] SRAM_Out;`
81			`reg [DATA_WIDTH-1:0] FLASH_Out_Tmp;`
82			`reg [DATA_WIDTH-1:0] SDRAM_Out_Tmp;`
83			`reg [DATA_WIDTH-1:0] SRAM_Out_Tmp;`
84			`reg LRCK_1X;`
85			`reg LRCK_2X;`
86			`reg LRCK_4X;`
87
88			`//////////// AUD_BCK Generator //////////////`
89			`always@(posedge iCLK_18_4 or negedge iRST_N)`
90			`begin`
91			`if(!iRST_N)`
92			`begin`
93			`BCK_DIV <= 0;`
94			`oAUD_BCK <= 0;`
95			`end`
96			`else`
97			`begin`
98			`if(BCK_DIV >= REF_CLK/(SAMPLE_RATEDATA_WIDTHCHANNEL_NUM*2)-1 )`
99			`begin`
100			`BCK_DIV <= 0;`
101			`oAUD_BCK <= ~oAUD_BCK;`
102			`end`
103			`else`
104			`BCK_DIV <= BCK_DIV+1;`
105			`end`
106			`end`
107			`//////////////////////////////////////////////////`
108			`//////////// AUD_LRCK Generator //////////////`
109			`always@(posedge iCLK_18_4 or negedge iRST_N)`
110			`begin`
111			`if(!iRST_N)`
112			`begin`
113			`LRCK_1X_DIV <= 0;`
114			`LRCK_2X_DIV <= 0;`
115			`LRCK_4X_DIV <= 0;`
116			`LRCK_1X <= 0;`
117			`LRCK_2X <= 0;`
118			`LRCK_4X <= 0;`
119			`end`
120			`else`
121			`begin`
122			`// LRCK 1X`
123			`if(LRCK_1X_DIV >= REF_CLK/(SAMPLE_RATE*2)-1 )`
124			`begin`
125			`LRCK_1X_DIV <= 0;`
126			`LRCK_1X <= ~LRCK_1X;`
127			`end`
128			`else`
129			`LRCK_1X_DIV <= LRCK_1X_DIV+1;`
130			`// LRCK 2X`
131			`if(LRCK_2X_DIV >= REF_CLK/(SAMPLE_RATE*4)-1 )`
132			`begin`
133			`LRCK_2X_DIV <= 0;`
134			`LRCK_2X <= ~LRCK_2X;`
135			`end`
136			`else`
137			`LRCK_2X_DIV <= LRCK_2X_DIV+1;`
138			`// LRCK 4X`
139			`if(LRCK_4X_DIV >= REF_CLK/(SAMPLE_RATE*8)-1 )`
140			`begin`
141			`LRCK_4X_DIV <= 0;`
142			`LRCK_4X <= ~LRCK_4X;`
143			`end`
144			`else`
145			`LRCK_4X_DIV <= LRCK_4X_DIV+1;`
146			`end`
147			`end`
148			`assign oAUD_LRCK = LRCK_1X;`
149			`//////////////////////////////////////////////////`
150			`////////// Sin LUT ADDR Generator //////////////`
151			`always@(negedge LRCK_1X or negedge iRST_N)`
152			`begin`
153			`if(!iRST_N)`
154			`SIN_Cont <= 0;`
155			`else`
156			`begin`
157			`if(SIN_Cont < SIN_SAMPLE_DATA-1 )`
158			`SIN_Cont <= SIN_Cont+1;`
159			`else`
160			`SIN_Cont <= 0;`
161			`end`
162			`end`
163			`//////////////////////////////////////////////////`
164			`////////// FLASH ADDR Generator //////////////`
165			`always@(negedge LRCK_4X or negedge iRST_N)`
166			`begin`
167			`if(!iRST_N)`
168			`FLASH_Cont <= 0;`
169			`else`
170			`begin`
171			`if(FLASH_Cont < FLASH_DATA_NUM-1 )`
172			`FLASH_Cont <= FLASH_Cont+1;`
173			`else`
174			`FLASH_Cont <= 0;`
175			`end`
176			`end`
177			`assign oFLASH_ADDR = FLASH_Cont;`
178			`//////////////////////////////////////////////////`
179			`////////// FLASH DATA Reorder //////////////`
180			`always@(posedge LRCK_4X or negedge iRST_N)`
181			`begin`
182			`if(!iRST_N)`
183			`FLASH_Out_Tmp <= 0;`
184			`else`
185			`begin`
186			`if(FLASH_Cont[0])`
187			`FLASH_Out_Tmp[15:8] <= iFLASH_DATA;`
188			`else`
189			`FLASH_Out_Tmp[7:0] <= iFLASH_DATA;`
190			`end`
191			`end`
192			`always@(negedge LRCK_2X or negedge iRST_N)`
193			`begin`
194			`if(!iRST_N)`
195			`FLASH_Out <= 0;`
196			`else`
197			`FLASH_Out <= FLASH_Out_Tmp;`
198			`end`
199			`//////////////////////////////////////////////////`
200			`////////// SDRAM ADDR Generator //////////////`
201			`always@(negedge LRCK_2X or negedge iRST_N)`
202			`begin`
203			`if(!iRST_N)`
204			`SDRAM_Cont <= 0;`
205			`else`
206			`begin`
207			`if(SDRAM_Cont < SDRAM_DATA_NUM-1 )`
208			`SDRAM_Cont <= SDRAM_Cont+1;`
209			`else`
210			`SDRAM_Cont <= 0;`
211			`end`
212			`end`
213			`assign oSDRAM_ADDR = SDRAM_Cont;`
214			`//////////////////////////////////////////////////`
215			`////////// SDRAM DATA Latch //////////////`
216			`always@(posedge LRCK_2X or negedge iRST_N)`
217			`begin`
218			`if(!iRST_N)`
219			`SDRAM_Out_Tmp <= 0;`
220			`else`
221			`SDRAM_Out_Tmp <= iSDRAM_DATA;`
222			`end`
223			`always@(negedge LRCK_2X or negedge iRST_N)`
224			`begin`
225			`if(!iRST_N)`
226			`SDRAM_Out <= 0;`
227			`else`
228			`SDRAM_Out <= SDRAM_Out_Tmp;`
229			`end`
230			`//////////////////////////////////////////////////`
231			`//////////// SRAM ADDR Generator ////////////`
232			`always@(negedge LRCK_2X or negedge iRST_N)`
233			`begin`
234			`if(!iRST_N)`
235			`SRAM_Cont <= 0;`
236			`else`
237			`begin`
238			`if(SRAM_Cont < SRAM_DATA_NUM-1 )`
239			`SRAM_Cont <= SRAM_Cont+1;`
240			`else`
241			`SRAM_Cont <= 0;`
242			`end`
243			`end`
244			`assign oSRAM_ADDR = SRAM_Cont;`
245			`//////////////////////////////////////////////////`
246			`////////// SRAM DATA Latch //////////////`
247			`always@(posedge LRCK_2X or negedge iRST_N)`
248			`begin`
249			`if(!iRST_N)`
250			`SRAM_Out_Tmp <= 0;`
251			`else`
252			`SRAM_Out_Tmp <= iSRAM_DATA;`
253			`end`
254			`always@(negedge LRCK_2X or negedge iRST_N)`
255			`begin`
256			`if(!iRST_N)`
257			`SRAM_Out <= 0;`
258			`else`
259			`SRAM_Out <= SRAM_Out_Tmp;`
260			`end`
261			`//////////////////////////////////////////////////`
262			`////////// 16 Bits PISO MSB First //////////////`
263			`always@(negedge oAUD_BCK or negedge iRST_N)`
264			`begin`
265			`if(!iRST_N)`
266			`SEL_Cont <= 0;`
267			`else`
268			`SEL_Cont <= SEL_Cont+1;`
269			`end`
270			`assign oAUD_DATA = (iSrc_Select==SIN_SANPLE) ? Sin_Out[~SEL_Cont] :`
271			`(iSrc_Select==FLASH_DATA) ? FLASH_Out[~SEL_Cont]:`
272			`(iSrc_Select==SDRAM_DATA) ? SDRAM_Out[~SEL_Cont]:`
273			`SRAM_Out[~SEL_Cont] ;`
274			`//////////////////////////////////////////////////`
275			`//////////// Sin Wave ROM Table //////////////`
276			`always@(SIN_Cont)`
277			`begin`
278			`case(SIN_Cont)`
279
280			`1 : Sin_Out <= 4276 ;`
281			`2 : Sin_Out <= 8480 ;`
282			`3 : Sin_Out <= 12539 ;`
283			`4 : Sin_Out <= 16383 ;`
284			`5 : Sin_Out <= 19947 ;`
285			`6 : Sin_Out <= 23169 ;`
286			`7 : Sin_Out <= 25995 ;`
287			`8 : Sin_Out <= 28377 ;`
288			`9 : Sin_Out <= 30272 ;`
289			`10 : Sin_Out <= 31650 ;`
290			`11 : Sin_Out <= 32486 ;`
291			`12 : Sin_Out <= 32767 ;`
292			`13 : Sin_Out <= 32486 ;`
293			`14 : Sin_Out <= 31650 ;`
294			`15 : Sin_Out <= 30272 ;`
295			`16 : Sin_Out <= 28377 ;`
296			`17 : Sin_Out <= 25995 ;`
297			`18 : Sin_Out <= 23169 ;`
298			`19 : Sin_Out <= 19947 ;`
299			`20 : Sin_Out <= 16383 ;`
300			`21 : Sin_Out <= 12539 ;`
301			`22 : Sin_Out <= 8480 ;`
302			`23 : Sin_Out <= 4276 ;`
303			`24 : Sin_Out <= 0 ;`
304			`25 : Sin_Out <= 61259 ;`
305			`26 : Sin_Out <= 57056 ;`
306			`27 : Sin_Out <= 52997 ;`
307			`28 : Sin_Out <= 49153 ;`
308			`29 : Sin_Out <= 45589 ;`
309			`30 : Sin_Out <= 42366 ;`
310			`31 : Sin_Out <= 39540 ;`
311			`32 : Sin_Out <= 37159 ;`
312			`33 : Sin_Out <= 35263 ;`
313			`34 : Sin_Out <= 33885 ;`
314			`35 : Sin_Out <= 33049 ;`
315			`36 : Sin_Out <= 32768 ;`
316			`37 : Sin_Out <= 33049 ;`
317			`38 : Sin_Out <= 33885 ;`
318			`39 : Sin_Out <= 35263 ;`
319			`40 : Sin_Out <= 37159 ;`
320			`41 : Sin_Out <= 39540 ;`
321			`42 : Sin_Out <= 42366 ;`
322			`43 : Sin_Out <= 45589 ;`
323			`44 : Sin_Out <= 49152 ;`
324			`45 : Sin_Out <= 52997 ;`
325			`46 : Sin_Out <= 57056 ;`
326			`47 : Sin_Out <= 61259 ;`
327			`default :`
328			`Sin_Out <= 0 ;`
329			`endcase`
330			`end`
331			`//////////////////////////////////////////////////`
332
333			`endmodule`
334
335
336
337