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tylerapohl |
//Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
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//use of Altera Corporation's design tools, logic functions and other
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//software and tools, and its AMPP partner logic functions, and any
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//output files any of the foregoing (including device programming or
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//simulation files), and any associated documentation or information are
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//expressly subject to the terms and conditions of the Altera Program
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//License Subscription Agreement or other applicable license agreement,
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//including, without limitation, that your use is for the sole purpose
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//of programming logic devices manufactured by Altera and sold by Altera
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//or its authorized distributors. Please refer to the applicable
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//agreement for further details.
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module CII_Starter_USB_API
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(
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//////////////////// Clock Input ////////////////////
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CLOCK_24, // 24 MHz
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CLOCK_27, // 27 MHz
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CLOCK_50, // 50 MHz
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EXT_CLOCK, // External Clock
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//////////////////// Push Button ////////////////////
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KEY, // Pushbutton[3:0]
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//////////////////// DPDT Switch ////////////////////
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SW, // Toggle Switch[9:0]
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//////////////////// 7-SEG Dispaly ////////////////////
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HEX0, // Seven Segment Digit 0
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HEX1, // Seven Segment Digit 1
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HEX2, // Seven Segment Digit 2
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HEX3, // Seven Segment Digit 3
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//////////////////////// LED ////////////////////////
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LEDG, // LED Green[7:0]
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LEDR, // LED Red[9:0]
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//////////////////////// UART ////////////////////////
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UART_TXD, // UART Transmitter
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UART_RXD, // UART Receiver
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///////////////////// SDRAM Interface ////////////////
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DRAM_DQ, // SDRAM Data bus 16 Bits
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DRAM_ADDR, // SDRAM Address bus 12 Bits
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DRAM_LDQM, // SDRAM Low-byte Data Mask
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DRAM_UDQM, // SDRAM High-byte Data Mask
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DRAM_WE_N, // SDRAM Write Enable
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DRAM_CAS_N, // SDRAM Column Address Strobe
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DRAM_RAS_N, // SDRAM Row Address Strobe
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DRAM_CS_N, // SDRAM Chip Select
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DRAM_BA_0, // SDRAM Bank Address 0
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DRAM_BA_1, // SDRAM Bank Address 0
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DRAM_CLK, // SDRAM Clock
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DRAM_CKE, // SDRAM Clock Enable
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//////////////////// Flash Interface ////////////////
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FL_DQ, // FLASH Data bus 8 Bits
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FL_ADDR, // FLASH Address bus 22 Bits
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FL_WE_N, // FLASH Write Enable
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FL_RST_N, // FLASH Reset
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FL_OE_N, // FLASH Output Enable
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FL_CE_N, // FLASH Chip Enable
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//////////////////// SRAM Interface ////////////////
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SRAM_DQ, // SRAM Data bus 16 Bits
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SRAM_ADDR, // SRAM Address bus 18 Bits
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SRAM_UB_N, // SRAM High-byte Data Mask
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SRAM_LB_N, // SRAM Low-byte Data Mask
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SRAM_WE_N, // SRAM Write Enable
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SRAM_CE_N, // SRAM Chip Enable
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SRAM_OE_N, // SRAM Output Enable
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//////////////////// SD_Card Interface ////////////////
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SD_DAT, // SD Card Data
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SD_DAT3, // SD Card Data 3
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SD_CMD, // SD Card Command Signal
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SD_CLK, // SD Card Clock
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//////////////////// USB JTAG link ////////////////////
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TDI, // CPLD -> FPGA (data in)
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TCK, // CPLD -> FPGA (clk)
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TCS, // CPLD -> FPGA (CS)
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TDO, // FPGA -> CPLD (data out)
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//////////////////// I2C ////////////////////////////
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I2C_SDAT, // I2C Data
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I2C_SCLK, // I2C Clock
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//////////////////// PS2 ////////////////////////////
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PS2_DAT, // PS2 Data
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PS2_CLK, // PS2 Clock
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//////////////////// VGA ////////////////////////////
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VGA_HS, // VGA H_SYNC
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VGA_VS, // VGA V_SYNC
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VGA_R, // VGA Red[3:0]
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VGA_G, // VGA Green[3:0]
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VGA_B, // VGA Blue[3:0]
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//////////////// Audio CODEC ////////////////////////
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AUD_ADCLRCK, // Audio CODEC ADC LR Clock
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AUD_ADCDAT, // Audio CODEC ADC Data
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AUD_DACLRCK, // Audio CODEC DAC LR Clock
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AUD_DACDAT, // Audio CODEC DAC Data
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AUD_BCLK, // Audio CODEC Bit-Stream Clock
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AUD_XCK, // Audio CODEC Chip Clock
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//////////////////// GPIO ////////////////////////////
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GPIO_0, // GPIO Connection 0
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GPIO_1 // GPIO Connection 1
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);
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//////////////////////// Clock Input ////////////////////////
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input [1:0] CLOCK_24; // 24 MHz
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input [1:0] CLOCK_27; // 27 MHz
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input CLOCK_50; // 50 MHz
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input EXT_CLOCK; // External Clock
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//////////////////////// Push Button ////////////////////////
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input [3:0] KEY; // Pushbutton[3:0]
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//////////////////////// DPDT Switch ////////////////////////
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input [9:0] SW; // Toggle Switch[9:0]
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//////////////////////// 7-SEG Dispaly ////////////////////////
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output [6:0] HEX0; // Seven Segment Digit 0
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output [6:0] HEX1; // Seven Segment Digit 1
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output [6:0] HEX2; // Seven Segment Digit 2
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output [6:0] HEX3; // Seven Segment Digit 3
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//////////////////////////// LED ////////////////////////////
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output [7:0] LEDG; // LED Green[7:0]
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output [9:0] LEDR; // LED Red[9:0]
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//////////////////////////// UART ////////////////////////////
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output UART_TXD; // UART Transmitter
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input UART_RXD; // UART Receiver
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/////////////////////// SDRAM Interface ////////////////////////
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inout [15:0] DRAM_DQ; // SDRAM Data bus 16 Bits
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output [11:0] DRAM_ADDR; // SDRAM Address bus 12 Bits
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output DRAM_LDQM; // SDRAM Low-byte Data Mask
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output DRAM_UDQM; // SDRAM High-byte Data Mask
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output DRAM_WE_N; // SDRAM Write Enable
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output DRAM_CAS_N; // SDRAM Column Address Strobe
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output DRAM_RAS_N; // SDRAM Row Address Strobe
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output DRAM_CS_N; // SDRAM Chip Select
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output DRAM_BA_0; // SDRAM Bank Address 0
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output DRAM_BA_1; // SDRAM Bank Address 0
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output DRAM_CLK; // SDRAM Clock
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output DRAM_CKE; // SDRAM Clock Enable
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//////////////////////// Flash Interface ////////////////////////
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inout [7:0] FL_DQ; // FLASH Data bus 8 Bits
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output [21:0] FL_ADDR; // FLASH Address bus 22 Bits
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output FL_WE_N; // FLASH Write Enable
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output FL_RST_N; // FLASH Reset
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output FL_OE_N; // FLASH Output Enable
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output FL_CE_N; // FLASH Chip Enable
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//////////////////////// SRAM Interface ////////////////////////
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inout [15:0] SRAM_DQ; // SRAM Data bus 16 Bits
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output [17:0] SRAM_ADDR; // SRAM Address bus 18 Bits
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output SRAM_UB_N; // SRAM High-byte Data Mask
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output SRAM_LB_N; // SRAM Low-byte Data Mask
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output SRAM_WE_N; // SRAM Write Enable
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output SRAM_CE_N; // SRAM Chip Enable
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output SRAM_OE_N; // SRAM Output Enable
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//////////////////// SD Card Interface ////////////////////////
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inout SD_DAT; // SD Card Data
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inout SD_DAT3; // SD Card Data 3
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inout SD_CMD; // SD Card Command Signal
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output SD_CLK; // SD Card Clock
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//////////////////////// I2C ////////////////////////////////
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inout I2C_SDAT; // I2C Data
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output I2C_SCLK; // I2C Clock
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//////////////////////// PS2 ////////////////////////////////
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input PS2_DAT; // PS2 Data
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input PS2_CLK; // PS2 Clock
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//////////////////// USB JTAG link ////////////////////////////
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input TDI; // CPLD -> FPGA (data in)
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input TCK; // CPLD -> FPGA (clk)
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input TCS; // CPLD -> FPGA (CS)
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output TDO; // FPGA -> CPLD (data out)
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//////////////////////// VGA ////////////////////////////
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output VGA_HS; // VGA H_SYNC
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output VGA_VS; // VGA V_SYNC
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output [3:0] VGA_R; // VGA Red[3:0]
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output [3:0] VGA_G; // VGA Green[3:0]
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output [3:0] VGA_B; // VGA Blue[3:0]
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//////////////////// Audio CODEC ////////////////////////////
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output AUD_ADCLRCK; // Audio CODEC ADC LR Clock
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input AUD_ADCDAT; // Audio CODEC ADC Data
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output AUD_DACLRCK; // Audio CODEC DAC LR Clock
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output AUD_DACDAT; // Audio CODEC DAC Data
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inout AUD_BCLK; // Audio CODEC Bit-Stream Clock
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output AUD_XCK; // Audio CODEC Chip Clock
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//////////////////////// GPIO ////////////////////////////////
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inout [35:0] GPIO_0; // GPIO Connection 0
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inout [35:0] GPIO_1; // GPIO Connection 1
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////////////////////////////////////////////////////////////////////
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// USB JTAG
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wire [7:0] mRXD_DATA,mTXD_DATA;
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wire mRXD_Ready,mTXD_Done,mTXD_Start;
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wire mTCK;
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// FLASH
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wire [21:0] mFL_ADDR;
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wire [7:0] mFL2RS_DATA,mRS2FL_DATA;
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wire [2:0] mFL_CMD;
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wire mFL_Ready,mFL_Start;
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// SDRAM
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wire [21:0] mSD_ADDR;
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wire [15:0] mSD2RS_DATA,mRS2SD_DATA;
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wire mSD_WR,mSD_RD,mSD_Done;
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// SRAM
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wire [17:0] mSR_ADDR;
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wire [15:0] mSR2RS_DATA,mRS2SR_DATA;
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wire mSR_OE,mSR_WE;
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// SEG7
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wire [31:0] mSEG7_DIG;
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// LCD
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wire [7:0] mLCD_DATA;
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wire mLCD_RS;
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wire mLCD_Start;
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wire mLCD_Done;
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// PS2
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wire [7:0] PS2_ASCII;
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wire PS2_Error,PS2_Ready;
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// VGA
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wire [9:0] mVGA_R;
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wire [9:0] mVGA_G;
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wire [9:0] mVGA_B;
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wire [9:0] mOSD_R;
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wire [9:0] mOSD_G;
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wire [9:0] mOSD_B;
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wire [9:0] mVIN_R;
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wire [9:0] mVIN_G;
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wire [9:0] mVIN_B;
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wire [9:0] oVGA_R;
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wire [9:0] oVGA_G;
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wire [9:0] oVGA_B;
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wire [9:0] mVGA_X;
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wire [9:0] mVGA_Y;
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wire [19:0] mVGA_ADDR;
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wire [9:0] mCursor_X;
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wire [9:0] mCursor_Y;
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wire [9:0] mCursor_R;
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wire [9:0] mCursor_G;
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wire [9:0] mCursor_B;
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wire [1:0] mOSD_CUR_EN;
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// Async Port Select
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wire [2:0] mSDR_Select;
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wire [2:0] mFL_Select;
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wire [2:0] mSR_Select;
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// FLASH Async Port
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wire [21:0] mFL_AS_ADDR_1;
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wire [21:0] mFL_AS_ADDR_2;
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wire [21:0] mFL_AS_ADDR_3;
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wire [7:0] mFL_AS_DATA_1;
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wire [7:0] mFL_AS_DATA_2;
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wire [7:0] mFL_AS_DATA_3;
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// SDRAM Async Port
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wire [15:0] mSDR_AS_DATAOUT_1;
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wire [15:0] mSDR_AS_DATAOUT_2;
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wire [15:0] mSDR_AS_DATAOUT_3;
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wire [21:0] mSDR_AS_ADDR_1 = 0;
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wire [21:0] mSDR_AS_ADDR_2 = 0;
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wire [21:0] mSDR_AS_ADDR_3 = 0;
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wire [15:0] mSDR_AS_DATAIN_1= 0;
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wire [15:0] mSDR_AS_DATAIN_2= 0;
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wire [15:0] mSDR_AS_DATAIN_3= 0;
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wire mSDR_AS_WR_n_1 = 0;
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wire mSDR_AS_WR_n_2 = 0;
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wire mSDR_AS_WR_n_3 = 0;
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// SRAM Async Port
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wire [15:0] mSRAM_VGA_DATA;
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wire VGA_CTRL_CLK;
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wire AUD_CTRL_CLK;
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wire DLY_RST;
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// All inout port turn to tri-state
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assign SD_DAT = 1'bz;
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assign GPIO_0 = 36'hzzzzzzzzz;
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assign GPIO_1 = 36'hzzzzzzzzz;
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// VGA Data Reorder
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assign mVIN_R = mVGA_ADDR[0] ? mSRAM_VGA_DATA[15:8]<<2 : mSRAM_VGA_DATA[7:0]<<2 ;
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assign mVIN_G = mVGA_ADDR[0] ? mSRAM_VGA_DATA[15:8]<<2 : mSRAM_VGA_DATA[7:0]<<2 ;
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assign mVIN_B = mVGA_ADDR[0] ? mSRAM_VGA_DATA[15:8]<<2 : mSRAM_VGA_DATA[7:0]<<2 ;
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// VGA Data Source Select
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assign mVGA_R = ~mOSD_CUR_EN[1] ? mOSD_R : mVIN_R;
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assign mVGA_G = ~mOSD_CUR_EN[1] ? mOSD_G : mVIN_G;
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assign mVGA_B = ~mOSD_CUR_EN[1] ? mOSD_B : mVIN_B;
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// VGA Data 10-bit to 4-bit
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assign VGA_R = oVGA_R[9:6];
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assign VGA_G = oVGA_G[9:6];
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assign VGA_B = oVGA_B[9:6];
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// Audio
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assign AUD_ADCLRCK = AUD_DACLRCK;
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assign AUD_XCK = AUD_CTRL_CLK;
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CLK_LOCK p0 ( .inclk(TCK),.outclk(mTCK) );
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Reset_Delay d0 ( .iCLK(CLOCK_50),.oRESET(DLY_RST) );
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SEG7_LUT_4 u0 ( HEX0,HEX1,HEX2,HEX3,mSEG7_DIG );
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USB_JTAG u1 ( // HOST
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.iTxD_DATA(mTXD_DATA),.oTxD_Done(mTXD_Done),.iTxD_Start(mTXD_Start),
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.oRxD_DATA(mRXD_DATA),.oRxD_Ready(mRXD_Ready),.iRST_n(KEY[0]),.iCLK(CLOCK_50),
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// JTAG
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| 290 |
|
|
.TDO(TDO),.TDI(TDI),.TCS(TCS),.TCK(mTCK) );
|
| 291 |
|
|
|
| 292 |
|
|
Multi_Flash u2 ( // Host Side
|
| 293 |
|
|
mFL2RS_DATA,mRS2FL_DATA,mFL_ADDR,mFL_CMD,mFL_Ready,mFL_Start,
|
| 294 |
|
|
// Async Side 1
|
| 295 |
|
|
mFL_AS_DATA_1,mFL_AS_ADDR_1,
|
| 296 |
|
|
// Async Side 2
|
| 297 |
|
|
mFL_AS_DATA_2,mFL_AS_ADDR_2,
|
| 298 |
|
|
// Async Side 3
|
| 299 |
|
|
mFL_AS_DATA_3,mFL_AS_ADDR_3,
|
| 300 |
|
|
// Control Signals
|
| 301 |
|
|
mFL_Select,CLOCK_50,KEY[0],
|
| 302 |
|
|
// Flash Interface
|
| 303 |
|
|
FL_DQ,FL_ADDR,FL_WE_N,FL_CE_N,FL_OE_N,FL_RST_N);
|
| 304 |
|
|
|
| 305 |
|
|
Multi_Sdram u3 ( // Host Side
|
| 306 |
|
|
mSD2RS_DATA,mRS2SD_DATA,mSD_ADDR,mSD_RD,mSD_WR,mSD_Done,
|
| 307 |
|
|
// Async Side 1
|
| 308 |
|
|
mSDR_AS_DATAOUT_1,mSDR_AS_DATAIN_1,mSDR_AS_ADDR_1,mSDR_AS_WR_n_1,
|
| 309 |
|
|
// Async Side 2
|
| 310 |
|
|
mSDR_AS_DATAOUT_2,mSDR_AS_DATAIN_2,mSDR_AS_ADDR_2,mSDR_AS_WR_n_2,
|
| 311 |
|
|
// Async Side 3
|
| 312 |
|
|
mSDR_AS_DATAOUT_3,mSDR_AS_DATAIN_3,mSDR_AS_ADDR_3,mSDR_AS_WR_n_3,
|
| 313 |
|
|
// Control Signals
|
| 314 |
|
|
mSDR_Select,CLOCK_50,KEY[0],
|
| 315 |
|
|
// SDRAM Interface
|
| 316 |
|
|
DRAM_ADDR,{DRAM_BA_1,DRAM_BA_0},DRAM_CS_N,DRAM_CKE,DRAM_RAS_N,
|
| 317 |
|
|
DRAM_CAS_N,DRAM_WE_N,DRAM_DQ,{DRAM_UDQM,DRAM_LDQM},DRAM_CLK);
|
| 318 |
|
|
|
| 319 |
|
|
ps2_keyboard u4 ( .clk(CLOCK_50),.reset(~KEY[0]),
|
| 320 |
|
|
.ps2_clk_i(PS2_CLK),.ps2_data_i(PS2_DAT),
|
| 321 |
|
|
.rx_ascii(PS2_ASCII),.rx_data_ready(PS2_Ready),
|
| 322 |
|
|
.rx_read(PS2_Ready) );
|
| 323 |
|
|
|
| 324 |
|
|
CMD_Decode u5 ( // USB JTAG
|
| 325 |
|
|
.iRXD_DATA(mRXD_DATA),.iRXD_Ready(mRXD_Ready),
|
| 326 |
|
|
.oTXD_DATA(mTXD_DATA),.oTXD_Start(mTXD_Start),.iTXD_Done(mTXD_Done),
|
| 327 |
|
|
// FLASH
|
| 328 |
|
|
.iFL_DATA(mFL2RS_DATA),.oFL_DATA(mRS2FL_DATA),
|
| 329 |
|
|
.oFL_ADDR(mFL_ADDR),.iFL_Ready(mFL_Ready),
|
| 330 |
|
|
.oFL_Start(mFL_Start),.oFL_CMD(mFL_CMD),
|
| 331 |
|
|
// SDRAM
|
| 332 |
|
|
.iSDR_DATA(mSD2RS_DATA),.oSDR_DATA(mRS2SD_DATA),
|
| 333 |
|
|
.oSDR_ADDR(mSD_ADDR),.iSDR_Done(mSD_Done),
|
| 334 |
|
|
.oSDR_WR(mSD_WR),.oSDR_RD(mSD_RD),
|
| 335 |
|
|
// SRAM
|
| 336 |
|
|
.iSR_DATA(mSR2RS_DATA),.oSR_DATA(mRS2SR_DATA),
|
| 337 |
|
|
.oSR_ADDR(mSR_ADDR),
|
| 338 |
|
|
.oSR_WE_N(mSR_WE),.oSR_OE_N(mSR_OE),
|
| 339 |
|
|
// LED + SEG7
|
| 340 |
|
|
.oLED_GREEN(LEDG),.oLED_RED(LEDR),
|
| 341 |
|
|
.oSEG7_DIG(mSEG7_DIG),
|
| 342 |
|
|
// VGA
|
| 343 |
|
|
.oCursor_X(mCursor_X),
|
| 344 |
|
|
.oCursor_Y(mCursor_Y),
|
| 345 |
|
|
.oCursor_R(mCursor_R),
|
| 346 |
|
|
.oCursor_G(mCursor_G),
|
| 347 |
|
|
.oCursor_B(mCursor_B),
|
| 348 |
|
|
.oOSD_CUR_EN(mOSD_CUR_EN),
|
| 349 |
|
|
// PS2
|
| 350 |
|
|
.iPS2_ScanCode(PS2_ASCII),.iPS2_Ready(PS2_Ready),
|
| 351 |
|
|
// Async Port Select
|
| 352 |
|
|
.oSDR_Select(mSDR_Select),
|
| 353 |
|
|
.oFL_Select(mFL_Select),
|
| 354 |
|
|
.oSR_Select(mSR_Select),
|
| 355 |
|
|
// Control
|
| 356 |
|
|
.iCLK(CLOCK_50),.iRST_n(KEY[0]) );
|
| 357 |
|
|
|
| 358 |
|
|
Multi_Sram u6 ( // Host Side
|
| 359 |
|
|
.oHS_DATA(mSR2RS_DATA),.iHS_DATA(mRS2SR_DATA),.iHS_ADDR(mSR_ADDR),
|
| 360 |
|
|
.iHS_WE_N(mSR_WE),.iHS_OE_N(mSR_OE),
|
| 361 |
|
|
// Async Side 1
|
| 362 |
|
|
.oAS1_DATA(mSRAM_VGA_DATA),.iAS1_ADDR(mVGA_ADDR[19:1]),
|
| 363 |
|
|
.iAS1_WE_N(1'b1),.iAS1_OE_N(1'b0),
|
| 364 |
|
|
// Control Signals
|
| 365 |
|
|
.iSelect(mSR_Select),.iRST_n(KEY[0]),
|
| 366 |
|
|
// SRAM
|
| 367 |
|
|
.SRAM_DQ(SRAM_DQ),
|
| 368 |
|
|
.SRAM_ADDR(SRAM_ADDR),
|
| 369 |
|
|
.SRAM_UB_N(SRAM_UB_N),
|
| 370 |
|
|
.SRAM_LB_N(SRAM_LB_N),
|
| 371 |
|
|
.SRAM_WE_N(SRAM_WE_N),
|
| 372 |
|
|
.SRAM_CE_N(SRAM_CE_N),
|
| 373 |
|
|
.SRAM_OE_N(SRAM_OE_N) );
|
| 374 |
|
|
|
| 375 |
|
|
VGA_Audio_PLL p1 ( .areset(~DLY_RST),.inclk0(CLOCK_27[0]),.c0(VGA_CTRL_CLK),.c1(AUD_CTRL_CLK) );
|
| 376 |
|
|
|
| 377 |
|
|
VGA_Controller u8 ( // Host Side
|
| 378 |
|
|
.iCursor_RGB_EN({mOSD_CUR_EN[0],3'h7}),
|
| 379 |
|
|
.iCursor_X(mCursor_X),
|
| 380 |
|
|
.iCursor_Y(mCursor_Y),
|
| 381 |
|
|
.iCursor_R(mCursor_R),
|
| 382 |
|
|
.iCursor_G(mCursor_G),
|
| 383 |
|
|
.iCursor_B(mCursor_B),
|
| 384 |
|
|
.oAddress(mVGA_ADDR),
|
| 385 |
|
|
.oCoord_X(mVGA_X),
|
| 386 |
|
|
.oCoord_Y(mVGA_Y),
|
| 387 |
|
|
.iRed(mVGA_R),
|
| 388 |
|
|
.iGreen(mVGA_G),
|
| 389 |
|
|
.iBlue(mVGA_B),
|
| 390 |
|
|
// VGA Side
|
| 391 |
|
|
.oVGA_R(oVGA_R),
|
| 392 |
|
|
.oVGA_G(oVGA_G),
|
| 393 |
|
|
.oVGA_B(oVGA_B),
|
| 394 |
|
|
.oVGA_H_SYNC(VGA_HS),
|
| 395 |
|
|
.oVGA_V_SYNC(VGA_VS),
|
| 396 |
|
|
// Control Signal
|
| 397 |
|
|
.iCLK(VGA_CTRL_CLK),
|
| 398 |
|
|
.iRST_N(DLY_RST) );
|
| 399 |
|
|
|
| 400 |
|
|
VGA_OSD_RAM u9 ( // Read Out Side
|
| 401 |
|
|
.oRed(mOSD_R),
|
| 402 |
|
|
.oGreen(mOSD_G),
|
| 403 |
|
|
.oBlue(mOSD_B),
|
| 404 |
|
|
.iVGA_ADDR(mVGA_ADDR),
|
| 405 |
|
|
.iVGA_X(mVGA_X),
|
| 406 |
|
|
.iVGA_Y(mVGA_Y),
|
| 407 |
|
|
.iVGA_CLK(VGA_CTRL_CLK),
|
| 408 |
|
|
// CLUT
|
| 409 |
|
|
.iON_R(1023),
|
| 410 |
|
|
.iON_G(1023),
|
| 411 |
|
|
.iON_B(1023),
|
| 412 |
|
|
.iOFF_R(0),
|
| 413 |
|
|
.iOFF_G(0),
|
| 414 |
|
|
.iOFF_B(512),
|
| 415 |
|
|
// Control Signals
|
| 416 |
|
|
.iRST_N(KEY[0]) );
|
| 417 |
|
|
|
| 418 |
|
|
I2C_AV_Config u10 ( // Host Side
|
| 419 |
|
|
.iCLK(CLOCK_50),
|
| 420 |
|
|
.iRST_N(KEY[0]),
|
| 421 |
|
|
// I2C Side
|
| 422 |
|
|
.I2C_SCLK(I2C_SCLK),
|
| 423 |
|
|
.I2C_SDAT(I2C_SDAT) );
|
| 424 |
|
|
|
| 425 |
|
|
AUDIO_DAC u11 ( // Memory Side
|
| 426 |
|
|
.oFLASH_ADDR(mFL_AS_ADDR_1),
|
| 427 |
|
|
.iFLASH_DATA(mFL_AS_DATA_1),
|
| 428 |
|
|
// Audio Side
|
| 429 |
|
|
.oAUD_BCK(AUD_BCLK),
|
| 430 |
|
|
.oAUD_DATA(AUD_DACDAT),
|
| 431 |
|
|
.oAUD_LRCK(AUD_DACLRCK),
|
| 432 |
|
|
// Control Signals
|
| 433 |
|
|
.iSrc_Select(SW[1:0]),
|
| 434 |
|
|
.iCLK_18_4(AUD_CTRL_CLK),
|
| 435 |
|
|
.iRST_N(DLY_RST) );
|
| 436 |
|
|
|
| 437 |
|
|
endmodule
|
