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[/] [z80control/] [trunk/] [CII_Starter_USB_API_v1/] [HW/] [CMD_Decode.v] - Blame information for rev 12

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//Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors.  Please refer to the applicable
//agreement for further details.
 
module CMD_Decode(      //      USB JTAG
                                        iRXD_DATA,oTXD_DATA,iRXD_Ready,iTXD_Done,oTXD_Start,
                                        //      LED
                                        oLED_RED,oLED_GREEN,
                                        //      7-SEG
                                        oSEG7_DIG,
                                        //      VGA
                                        oOSD_CUR_EN,oCursor_X,oCursor_Y,
                                        oCursor_R,oCursor_G,oCursor_B,
                                        //      FLASH
                                        oFL_DATA,iFL_DATA,oFL_ADDR,iFL_Ready,oFL_Start,oFL_CMD,
                                        //      SDRAM
                                        oSDR_DATA,iSDR_DATA,oSDR_ADDR,iSDR_Done,oSDR_WR,oSDR_RD,
                                        //      SRAM
                                        oSR_DATA,iSR_DATA,oSR_ADDR,oSR_WE_N,oSR_OE_N,
                                        //      PS2
                                        iPS2_ScanCode,iPS2_Ready,
                                        //      Async Port Select
                                        oSDR_Select,oFL_Select,oSR_Select,
                                        //      Control
                                        iCLK,iRST_n     );
//      USB JTAG
input [7:0] iRXD_DATA;
input iRXD_Ready,iTXD_Done;
output [7:0] oTXD_DATA;
output oTXD_Start;
//      LED
output reg [17:0] oLED_RED;
output reg [8:0]  oLED_GREEN;
//      7-SEG
output reg [31:0] oSEG7_DIG;
//      VGA
output reg [9:0] oCursor_X;
output reg [9:0] oCursor_Y;
output reg [9:0] oCursor_R;
output reg [9:0] oCursor_G;
output reg [9:0] oCursor_B;
output reg [1:0] oOSD_CUR_EN;
//      FLASH
input [7:0] iFL_DATA;
input iFL_Ready;
output reg [21:0] oFL_ADDR;
output reg [7:0] oFL_DATA;
output reg [2:0] oFL_CMD;
output reg oFL_Start;
//      SDRAM
input [15:0] iSDR_DATA;
input iSDR_Done;
output reg [21:0] oSDR_ADDR;
output reg [15:0] oSDR_DATA;
output oSDR_WR,oSDR_RD;
//      SRAM
input   [15:0]   iSR_DATA;
output  reg [15:0]       oSR_DATA;
output  reg     [17:0]   oSR_ADDR;
output  oSR_WE_N,oSR_OE_N;
//      PS2
input [7:0] iPS2_ScanCode;
input iPS2_Ready;
//      Async Port Select
output reg [1:0] oSDR_Select;
output reg [1:0] oFL_Select;
output reg [1:0] oSR_Select;
//      Control
input iCLK,iRST_n;
 
//      Internal Register
reg [63:0] CMD_Tmp;
reg [2:0] mFL_ST,mSDR_ST,mPS2_ST,mSR_ST,mLCD_ST;
//      SDRAM Control Register
reg mSDR_WRn,mSDR_Start;
//      SRAM Control Register
reg     mSR_WRn,mSR_Start;
//      Active Flag
reg f_SETUP,f_LED,f_SEG7,f_SDR_SEL,f_FL_SEL,f_SR_SEL;
reg     f_FLASH,f_SDRAM,f_PS2,f_SRAM,f_VGA;
//      USB JTAG TXD Output
reg oFL_TXD_Start,oSDR_TXD_Start,oPS2_TXD_Start,oSR_TXD_Start;
reg [7:0] oFL_TXD_DATA,oSDR_TXD_DATA,oPS2_TXD_DATA,oSR_TXD_DATA;
//      TXD Output Select Register
reg sel_FL,sel_SDR,sel_PS2,sel_SR;
 
 
wire [7:0]       CMD_Action      =       CMD_Tmp[63:56];
wire [7:0]       CMD_Target      =       CMD_Tmp[55:48];
wire [23:0]      CMD_ADDR        =       CMD_Tmp[47:24];
wire [15:0]      CMD_DATA        =       CMD_Tmp[23: 8];
wire [7:0]       CMD_MODE        =       CMD_Tmp[ 7: 0];
wire [7:0]       Pre_Target      =       CMD_Tmp[47:40];
 
`include "RS232_Command.h"
`include "Flash_Command.h"
 
////////////////         SDRAM Select   /////////////////////
always@(posedge iCLK or negedge iRST_n)
begin
        if(!iRST_n)
        begin
                oSDR_Select     <=0;
                f_SDR_SEL       <=0;
        end
        else
        begin
                if(iRXD_Ready && (Pre_Target == SDRSEL) )
                f_SDR_SEL<=1;
                if(f_SDR_SEL)
                begin
                        if( (CMD_Action == SETUP) && (CMD_MODE  == OUTSEL) &&
                                (CMD_ADDR == 24'h123456) )
                        oSDR_Select<=CMD_DATA[1:0];
                        f_SDR_SEL<=0;
                end
        end
end
/////////////////////////////////////////////////////////
////////////////         FLASH Select   /////////////////////
always@(posedge iCLK or negedge iRST_n)
begin
        if(!iRST_n)
        begin
                oFL_Select      <=0;
                f_FL_SEL        <=0;
        end
        else
        begin
                if(iRXD_Ready && (Pre_Target == FLSEL) )
                f_FL_SEL<=1;
                if(f_FL_SEL)
                begin
                        if( (CMD_Action == SETUP) && (CMD_MODE  == OUTSEL) &&
                                (CMD_ADDR == 24'h123456) )
                        oFL_Select<=CMD_DATA[1:0];
                        f_FL_SEL<=0;
                end
        end
end
/////////////////////////////////////////////////////////
////////////////         SRAM Select    /////////////////////
always@(posedge iCLK or negedge iRST_n)
begin
        if(!iRST_n)
        begin
                oSR_Select      <=0;
                f_SR_SEL        <=0;
        end
        else
        begin
                if(iRXD_Ready && (Pre_Target == SRSEL) )
                f_SR_SEL<=1;
                if(f_SR_SEL)
                begin
                        if( (CMD_Action == SETUP) && (CMD_MODE  == OUTSEL) &&
                                (CMD_ADDR == 24'h123456) )
                        oSR_Select<=CMD_DATA[1:0];
                        f_SR_SEL<=0;
                end
        end
end
/////////////////////////////////////////////////////////
/////////////////       TXD     Output Select           /////////////
always@(posedge iCLK or negedge iRST_n)
begin
        if(!iRST_n)
        begin
                sel_FL<=0;
                sel_SDR<=0;
                sel_PS2<=0;
                sel_SR<=0;
                f_SETUP<=0;
        end
        else
        begin
                if(iRXD_Ready && (Pre_Target == SET_REG) )
                f_SETUP<=1;
                if(f_SETUP)
                begin
                        if( (CMD_Action == SETUP) && (CMD_MODE  == OUTSEL) &&
                                (CMD_ADDR == 24'h123456) )
                        begin
                                case(CMD_DATA[7:0])
                                FLASH:  begin
                                                        sel_FL  <=1;
                                                        sel_SDR <=0;
                                                        sel_PS2 <=0;
                                                        sel_SR  <=0;
                                                end
                                SDRAM:  begin
                                                        sel_FL  <=0;
                                                        sel_SDR <=1;
                                                        sel_PS2 <=0;
                                                        sel_SR  <=0;
                                                end
                                PS2:    begin
                                                        sel_FL  <=0;
                                                        sel_SDR <=0;
                                                        sel_PS2 <=1;
                                                        sel_SR  <=0;
                                                end
                                SRAM:   begin
                                                        sel_FL  <=0;
                                                        sel_SDR <=0;
                                                        sel_PS2 <=0;
                                                        sel_SR  <=1;
                                                end
                                endcase
                        end
                        f_SETUP<=0;
                end
        end
end
assign oTXD_Start       =       (sel_FL)        ?       oFL_TXD_Start   :
                                                (sel_SDR)       ?       oSDR_TXD_Start  :
                                                (sel_SR)        ?       oSR_TXD_Start   :
                                                                                oPS2_TXD_Start  ;
assign oTXD_DATA        =       (sel_FL)        ?       oFL_TXD_DATA    :
                                                (sel_SDR)       ?       oSDR_TXD_DATA   :
                                                (sel_SR)        ?       oSR_TXD_DATA    :
                                                                                oPS2_TXD_DATA   ;
/////////////////////////////////////////////////////////
///////         Shift Register For Command Temp /////////////
always@(posedge iCLK or negedge iRST_n)
begin
        if(!iRST_n)
        CMD_Tmp<=0;
        else
        begin
                if(iRXD_Ready)
                CMD_Tmp<={CMD_Tmp[55:0],iRXD_DATA};
        end
end
/////////////////////////////////////////////////////////
////////////////         LED Control    /////////////////////
always@(posedge iCLK or negedge iRST_n)
begin
        if(!iRST_n)
        begin
                oLED_RED        <=0;
                oLED_GREEN      <=0;
                f_LED           <=0;
        end
        else
        begin
                if(iRXD_Ready && (Pre_Target == LED) )
                f_LED<=1;
                if(f_LED)
                begin
                        if( (CMD_Action == WRITE) && (CMD_MODE  == DISPLAY) )
                        begin
                                oLED_RED        <=CMD_ADDR;
                                oLED_GREEN      <=CMD_DATA;
                        end
                        f_LED<=0;
                end
        end
end
/////////////////////////////////////////////////////////
////////////////        7-SEG Control   /////////////////////
always@(posedge iCLK or negedge iRST_n)
begin
        if(!iRST_n)
        begin
                oSEG7_DIG<=0;
                f_SEG7<=0;
        end
        else
        begin
                if(iRXD_Ready  && (Pre_Target == SEG7) )
                f_SEG7<=1;
                if(f_SEG7)
                begin
                        if( (CMD_Action == WRITE) && (CMD_MODE  == DISPLAY) )
                        oSEG7_DIG<={CMD_ADDR[15:0],CMD_DATA};
                        f_SEG7<=0;
                end
        end
end
/////////////////////////////////////////////////////////
////////////////        Flash Control   /////////////////////
always@(posedge iCLK or negedge iRST_n)
begin
        if(!iRST_n)
        begin
                oFL_TXD_Start   <=0;
                oFL_Start               <=0;
                f_FLASH                 <=0;
                mFL_ST                  <=0;
        end
        else
        begin
                if( CMD_Action == READ )
                oFL_CMD         <=      CMD_READ;
                else if( CMD_Action == WRITE )
                oFL_CMD         <=      CMD_WRITE;
                else if( CMD_Action == ERASE )
                oFL_CMD         <=      CMD_CHP_ERA;
                else
                oFL_CMD         <=      3'b000;
 
                if(iRXD_Ready && (Pre_Target == FLASH))
                f_FLASH<=1;
                if(f_FLASH)
                begin
                        case(mFL_ST)
                        0:       begin
                                        if( (CMD_MODE   == NORMAL) && (CMD_Target == FLASH) && (CMD_DATA[15:8] == 8'hFF) )
                                        begin
                                                oFL_ADDR        <=      CMD_ADDR;
                                                oFL_DATA        <=      CMD_DATA;
                                                oFL_Start<=     1;
                                                mFL_ST  <=      1;
                                        end
                                        else
                                        begin
                                                mFL_ST  <=      0;
                                                f_FLASH <=      0;
                                        end
                                end
                        1:      begin
                                        if(iFL_Ready)
                                        begin
                                                mFL_ST<=2;
                                                oFL_Start<=0;
                                        end
                                end
                        2:      begin
                                        oFL_Start<=1;
                                        mFL_ST<=3;
                                end
                        3:      begin
                                        if(iFL_Ready)
                                        begin
                                                mFL_ST<=4;
                                                oFL_Start<=0;
                                        end
                                end
                        4:      begin
                                        oFL_Start<=1;
                                        mFL_ST<=5;
                                end
                        5:      begin
                                        if(iFL_Ready)
                                        begin
                                                if( (oFL_CMD == CMD_READ) )
                                                        mFL_ST  <=      6;
                                                else
                                                begin
                                                        mFL_ST  <=      0;
                                                        f_FLASH <=      0;
                                                end
                                                oFL_Start       <=      0;
                                        end
                                end
                        6:      begin
                                        oFL_TXD_DATA    <=      iFL_DATA;
                                        oFL_TXD_Start   <=      1;
                                        mFL_ST                  <=      7;
                                end
                        7:      begin
                                        if(iTXD_Done)
                                        begin
                                                oFL_TXD_Start<=0;
                                                mFL_ST  <=      0;
                                                f_FLASH <=      0;
                                        end
                                end
                        endcase
                end
        end
end
/////////////////////////////////////////////////////////
/////////////////       PS2 Control             /////////////////////
always@(posedge iCLK or negedge iRST_n)
begin
        if(!iRST_n)
        begin
                oPS2_TXD_Start<=0;
                f_PS2<=0;
                mPS2_ST<=0;
        end
        else
        begin
                if(iPS2_Ready && iPS2_ScanCode!=8'h2e)
                begin
                        f_PS2<=1;
                        oPS2_TXD_DATA<=iPS2_ScanCode;
                end
                if(f_PS2)
                begin
                        case(mPS2_ST)
                        0:       begin
                                        oPS2_TXD_Start  <=1;
                                        mPS2_ST                 <=1;
                                end
                        1:      begin
                                        if(iTXD_Done)
                                        begin
                                                oPS2_TXD_Start  <=0;
                                                mPS2_ST                 <=0;
                                                f_PS2                   <=0;
                                        end
                                end
                        endcase
                end
        end
end
/////////////////////////////////////////////////////////
////////////////        Sdram Control   /////////////////////
always@(posedge iCLK or negedge iRST_n)
begin
        if(!iRST_n)
        begin
                oSDR_TXD_Start  <=0;
                mSDR_WRn                <=0;
                mSDR_Start              <=0;
                f_SDRAM                 <=0;
                mSDR_ST                 <=0;
        end
        else
        begin
                if( CMD_Action == READ )
                mSDR_WRn        <=      1'b0;
                else if( CMD_Action == WRITE )
                mSDR_WRn        <=      1'b1;
 
                if(iRXD_Ready && (Pre_Target == SDRAM))
                f_SDRAM<=1;
                if(f_SDRAM)
                begin
                        case(mSDR_ST)
                        0:       begin
                                        if( (CMD_MODE   == NORMAL) && (CMD_Target == SDRAM) )
                                        begin
                                                oSDR_ADDR       <=      CMD_ADDR;
                                                oSDR_DATA       <=      CMD_DATA;
                                                mSDR_Start      <=      1;
                                                mSDR_ST         <=      1;
                                        end
                                        else
                                        begin
                                                mSDR_ST <=      0;
                                                f_SDRAM <=      0;
                                        end
                                end
                        1:      begin
                                        if(iSDR_Done)
                                        begin
                                                if(mSDR_WRn == 1'b0)
                                                        mSDR_ST <=      2;
                                                else
                                                begin
                                                        mSDR_ST <=      0;
                                                        f_SDRAM <=      0;
                                                        mSDR_Start      <=      0;
                                                end
                                        end
                                end
                        2:      begin
                                        oSDR_TXD_DATA   <= iSDR_DATA[7:0];
                                        oSDR_TXD_Start  <=      1;
                                        mSDR_ST                 <=      3;
                                end
                        3:      begin
                                        if(iTXD_Done)
                                        begin
                                                oSDR_TXD_Start<=0;
                                                mSDR_ST <=      4;
                                        end
                                end
                        4:      begin
                                        oSDR_TXD_DATA   <=      iSDR_DATA[15:8];
                                        oSDR_TXD_Start  <=      1;
                                        mSDR_ST                 <=      5;
                                end
                        5:      begin
                                        if(iTXD_Done)
                                        begin
                                                mSDR_Start      <=      0;
                                                oSDR_TXD_Start<=0;
                                                mSDR_ST <=      0;
                                                f_SDRAM <=      0;
                                        end
                                end
                        endcase
                end
        end
end
 
assign  oSDR_WR =       mSDR_WRn & mSDR_Start;
assign  oSDR_RD =       ~mSDR_WRn & mSDR_Start;
/////////////////////////////////////////////////////////
////////////////        SRAM Control    /////////////////////
always@(posedge iCLK or negedge iRST_n)
begin
        if(!iRST_n)
        begin
                oSR_TXD_Start   <=0;
                mSR_WRn                 <=0;
                mSR_Start               <=0;
                f_SRAM                  <=0;
                mSR_ST                  <=0;
        end
        else
        begin
                if( CMD_Action == READ )
                mSR_WRn <=      1'b0;
                else if( CMD_Action == WRITE )
                mSR_WRn <=      1'b1;
 
                if(iRXD_Ready && (Pre_Target == SRAM))
                f_SRAM<=1;
                if(f_SRAM)
                begin
                        case(mSR_ST)
                        0:       begin
                                        if( (CMD_MODE   == NORMAL) && (CMD_Target == SRAM) )
                                        begin
                                                oSR_ADDR        <=      CMD_ADDR;
                                                oSR_DATA        <=      CMD_DATA;
                                                mSR_Start       <=      1;
                                                mSR_ST          <=      1;
                                        end
                                        else
                                        begin
                                                mSR_ST  <=      0;
                                                f_SRAM  <=      0;
                                        end
                                end
                        1:      begin
                                        if(mSR_WRn == 1'b0)
                                                mSR_ST  <=      2;
                                        else
                                        begin
                                                mSR_ST  <=      0;
                                                f_SRAM  <=      0;
                                                mSR_Start       <=      0;
                                        end
                                end
                        2:      begin
                                        oSR_TXD_DATA    <=      iSR_DATA[7:0];
                                        oSR_TXD_Start   <=      1;
                                        mSR_ST                  <=      3;
                                end
                        3:      begin
                                        if(iTXD_Done)
                                        begin
                                                oSR_TXD_Start<=0;
                                                mSR_ST  <=      4;
                                        end
                                end
                        4:      begin
                                        oSR_TXD_DATA    <=      iSR_DATA[15:8];
                                        oSR_TXD_Start   <=      1;
                                        mSR_ST                  <=      5;
                                end
                        5:      begin
                                        if(iTXD_Done)
                                        begin
                                                mSR_Start       <=      0;
                                                oSR_TXD_Start<= 0;
                                                mSR_ST          <=      0;
                                                f_SRAM          <=      0;
                                        end
                                end
                        endcase
                end
        end
end
 
assign  oSR_OE_N        =       ~(~mSR_WRn & mSR_Start );
assign  oSR_WE_N        =       ~( mSR_WRn & mSR_Start );
 
/////////////////////////////////////////////////////////
////////////////////   VGA Control      /////////////////////
always@(posedge iCLK or negedge iRST_n)
begin
        if(!iRST_n)
        begin
                oCursor_X       <=      0;
                oCursor_Y       <=      0;
                oCursor_R       <=      0;
                oCursor_G       <=      0;
                oCursor_B       <=      0;
                oOSD_CUR_EN     <=      0;
                f_VGA           <=      0;
        end
        else
        begin
                if(iRXD_Ready  && (Pre_Target == VGA) )
                f_VGA<=1;
                if(f_VGA)
                begin
                        if( (CMD_Action == WRITE) && (CMD_MODE  == DISPLAY) )
                        begin
                                case(CMD_ADDR[2:0])
                                0:       oOSD_CUR_EN     <=      CMD_DATA[1:0];
                                1:      oCursor_X       <=      CMD_DATA[9:0];
                                2:      oCursor_Y       <=      CMD_DATA[9:0];
                                3:      oCursor_R       <=      CMD_DATA[9:0];
                                4:      oCursor_G       <=      CMD_DATA[9:0];
                                5:      oCursor_B       <=      CMD_DATA[9:0];
                                endcase
                        end
                        f_VGA<=0;
                end
        end
end
/////////////////////////////////////////////////////////
 
endmodule

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Subversion Repositories z80control

[/] [z80control/] [trunk/] [CII_Starter_USB_API_v1/] [HW/] [CMD_Decode.v] - Blame information for rev 12

Line No.	Rev	Author	Line
1	12	tylerapohl	`//Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your`
2			`//use of Altera Corporation's design tools, logic functions and other`
3			`//software and tools, and its AMPP partner logic functions, and any`
4			`//output files any of the foregoing (including device programming or`
5			`//simulation files), and any associated documentation or information are`
6			`//expressly subject to the terms and conditions of the Altera Program`
7			`//License Subscription Agreement or other applicable license agreement,`
8			`//including, without limitation, that your use is for the sole purpose`
9			`//of programming logic devices manufactured by Altera and sold by Altera`
10			`//or its authorized distributors. Please refer to the applicable`
11			`//agreement for further details.`
12
13			`module CMD_Decode( // USB JTAG`
14			`iRXD_DATA,oTXD_DATA,iRXD_Ready,iTXD_Done,oTXD_Start,`
15			`// LED`
16			`oLED_RED,oLED_GREEN,`
17			`// 7-SEG`
18			`oSEG7_DIG,`
19			`// VGA`
20			`oOSD_CUR_EN,oCursor_X,oCursor_Y,`
21			`oCursor_R,oCursor_G,oCursor_B,`
22			`// FLASH`
23			`oFL_DATA,iFL_DATA,oFL_ADDR,iFL_Ready,oFL_Start,oFL_CMD,`
24			`// SDRAM`
25			`oSDR_DATA,iSDR_DATA,oSDR_ADDR,iSDR_Done,oSDR_WR,oSDR_RD,`
26			`// SRAM`
27			`oSR_DATA,iSR_DATA,oSR_ADDR,oSR_WE_N,oSR_OE_N,`
28			`// PS2`
29			`iPS2_ScanCode,iPS2_Ready,`
30			`// Async Port Select`
31			`oSDR_Select,oFL_Select,oSR_Select,`
32			`// Control`
33			`iCLK,iRST_n );`
34			`// USB JTAG`
35			`input [7:0] iRXD_DATA;`
36			`input iRXD_Ready,iTXD_Done;`
37			`output [7:0] oTXD_DATA;`
38			`output oTXD_Start;`
39			`// LED`
40			`output reg [17:0] oLED_RED;`
41			`output reg [8:0] oLED_GREEN;`
42			`// 7-SEG`
43			`output reg [31:0] oSEG7_DIG;`
44			`// VGA`
45			`output reg [9:0] oCursor_X;`
46			`output reg [9:0] oCursor_Y;`
47			`output reg [9:0] oCursor_R;`
48			`output reg [9:0] oCursor_G;`
49			`output reg [9:0] oCursor_B;`
50			`output reg [1:0] oOSD_CUR_EN;`
51			`// FLASH`
52			`input [7:0] iFL_DATA;`
53			`input iFL_Ready;`
54			`output reg [21:0] oFL_ADDR;`
55			`output reg [7:0] oFL_DATA;`
56			`output reg [2:0] oFL_CMD;`
57			`output reg oFL_Start;`
58			`// SDRAM`
59			`input [15:0] iSDR_DATA;`
60			`input iSDR_Done;`
61			`output reg [21:0] oSDR_ADDR;`
62			`output reg [15:0] oSDR_DATA;`
63			`output oSDR_WR,oSDR_RD;`
64			`// SRAM`
65			`input [15:0] iSR_DATA;`
66			`output reg [15:0] oSR_DATA;`
67			`output reg [17:0] oSR_ADDR;`
68			`output oSR_WE_N,oSR_OE_N;`
69			`// PS2`
70			`input [7:0] iPS2_ScanCode;`
71			`input iPS2_Ready;`
72			`// Async Port Select`
73			`output reg [1:0] oSDR_Select;`
74			`output reg [1:0] oFL_Select;`
75			`output reg [1:0] oSR_Select;`
76			`// Control`
77			`input iCLK,iRST_n;`
78
79			`// Internal Register`
80			`reg [63:0] CMD_Tmp;`
81			`reg [2:0] mFL_ST,mSDR_ST,mPS2_ST,mSR_ST,mLCD_ST;`
82			`// SDRAM Control Register`
83			`reg mSDR_WRn,mSDR_Start;`
84			`// SRAM Control Register`
85			`reg mSR_WRn,mSR_Start;`
86			`// Active Flag`
87			`reg f_SETUP,f_LED,f_SEG7,f_SDR_SEL,f_FL_SEL,f_SR_SEL;`
88			`reg f_FLASH,f_SDRAM,f_PS2,f_SRAM,f_VGA;`
89			`// USB JTAG TXD Output`
90			`reg oFL_TXD_Start,oSDR_TXD_Start,oPS2_TXD_Start,oSR_TXD_Start;`
91			`reg [7:0] oFL_TXD_DATA,oSDR_TXD_DATA,oPS2_TXD_DATA,oSR_TXD_DATA;`
92			`// TXD Output Select Register`
93			`reg sel_FL,sel_SDR,sel_PS2,sel_SR;`
94
95
96			`wire [7:0] CMD_Action = CMD_Tmp[63:56];`
97			`wire [7:0] CMD_Target = CMD_Tmp[55:48];`
98			`wire [23:0] CMD_ADDR = CMD_Tmp[47:24];`
99			`wire [15:0] CMD_DATA = CMD_Tmp[23: 8];`
100			`wire [7:0] CMD_MODE = CMD_Tmp[ 7: 0];`
101			`wire [7:0] Pre_Target = CMD_Tmp[47:40];`
102
103			`include "RS232_Command.h"
104			`include "Flash_Command.h"
105
106			`//////////////// SDRAM Select /////////////////////`
107			`always@(posedge iCLK or negedge iRST_n)`
108			`begin`
109			`if(!iRST_n)`
110			`begin`
111			`oSDR_Select <=0;`
112			`f_SDR_SEL <=0;`
113			`end`
114			`else`
115			`begin`
116			`if(iRXD_Ready && (Pre_Target == SDRSEL) )`
117			`f_SDR_SEL<=1;`
118			`if(f_SDR_SEL)`
119			`begin`
120			`if( (CMD_Action == SETUP) && (CMD_MODE == OUTSEL) &&`
121			`(CMD_ADDR == 24'h123456) )`
122			`oSDR_Select<=CMD_DATA[1:0];`
123			`f_SDR_SEL<=0;`
124			`end`
125			`end`
126			`end`
127			`/////////////////////////////////////////////////////////`
128			`//////////////// FLASH Select /////////////////////`
129			`always@(posedge iCLK or negedge iRST_n)`
130			`begin`
131			`if(!iRST_n)`
132			`begin`
133			`oFL_Select <=0;`
134			`f_FL_SEL <=0;`
135			`end`
136			`else`
137			`begin`
138			`if(iRXD_Ready && (Pre_Target == FLSEL) )`
139			`f_FL_SEL<=1;`
140			`if(f_FL_SEL)`
141			`begin`
142			`if( (CMD_Action == SETUP) && (CMD_MODE == OUTSEL) &&`
143			`(CMD_ADDR == 24'h123456) )`
144			`oFL_Select<=CMD_DATA[1:0];`
145			`f_FL_SEL<=0;`
146			`end`
147			`end`
148			`end`
149			`/////////////////////////////////////////////////////////`
150			`//////////////// SRAM Select /////////////////////`
151			`always@(posedge iCLK or negedge iRST_n)`
152			`begin`
153			`if(!iRST_n)`
154			`begin`
155			`oSR_Select <=0;`
156			`f_SR_SEL <=0;`
157			`end`
158			`else`
159			`begin`
160			`if(iRXD_Ready && (Pre_Target == SRSEL) )`
161			`f_SR_SEL<=1;`
162			`if(f_SR_SEL)`
163			`begin`
164			`if( (CMD_Action == SETUP) && (CMD_MODE == OUTSEL) &&`
165			`(CMD_ADDR == 24'h123456) )`
166			`oSR_Select<=CMD_DATA[1:0];`
167			`f_SR_SEL<=0;`
168			`end`
169			`end`
170			`end`
171			`/////////////////////////////////////////////////////////`
172			`///////////////// TXD Output Select /////////////`
173			`always@(posedge iCLK or negedge iRST_n)`
174			`begin`
175			`if(!iRST_n)`
176			`begin`
177			`sel_FL<=0;`
178			`sel_SDR<=0;`
179			`sel_PS2<=0;`
180			`sel_SR<=0;`
181			`f_SETUP<=0;`
182			`end`
183			`else`
184			`begin`
185			`if(iRXD_Ready && (Pre_Target == SET_REG) )`
186			`f_SETUP<=1;`
187			`if(f_SETUP)`
188			`begin`
189			`if( (CMD_Action == SETUP) && (CMD_MODE == OUTSEL) &&`
190			`(CMD_ADDR == 24'h123456) )`
191			`begin`
192			`case(CMD_DATA[7:0])`
193			`FLASH: begin`
194			`sel_FL <=1;`
195			`sel_SDR <=0;`
196			`sel_PS2 <=0;`
197			`sel_SR <=0;`
198			`end`
199			`SDRAM: begin`
200			`sel_FL <=0;`
201			`sel_SDR <=1;`
202			`sel_PS2 <=0;`
203			`sel_SR <=0;`
204			`end`
205			`PS2: begin`
206			`sel_FL <=0;`
207			`sel_SDR <=0;`
208			`sel_PS2 <=1;`
209			`sel_SR <=0;`
210			`end`
211			`SRAM: begin`
212			`sel_FL <=0;`
213			`sel_SDR <=0;`
214			`sel_PS2 <=0;`
215			`sel_SR <=1;`
216			`end`
217			`endcase`
218			`end`
219			`f_SETUP<=0;`
220			`end`
221			`end`
222			`end`
223			`assign oTXD_Start = (sel_FL) ? oFL_TXD_Start :`
224			`(sel_SDR) ? oSDR_TXD_Start :`
225			`(sel_SR) ? oSR_TXD_Start :`
226			`oPS2_TXD_Start ;`
227			`assign oTXD_DATA = (sel_FL) ? oFL_TXD_DATA :`
228			`(sel_SDR) ? oSDR_TXD_DATA :`
229			`(sel_SR) ? oSR_TXD_DATA :`
230			`oPS2_TXD_DATA ;`
231			`/////////////////////////////////////////////////////////`
232			`/////// Shift Register For Command Temp /////////////`
233			`always@(posedge iCLK or negedge iRST_n)`
234			`begin`
235			`if(!iRST_n)`
236			`CMD_Tmp<=0;`
237			`else`
238			`begin`
239			`if(iRXD_Ready)`
240			`CMD_Tmp<={CMD_Tmp[55:0],iRXD_DATA};`
241			`end`
242			`end`
243			`/////////////////////////////////////////////////////////`
244			`//////////////// LED Control /////////////////////`
245			`always@(posedge iCLK or negedge iRST_n)`
246			`begin`
247			`if(!iRST_n)`
248			`begin`
249			`oLED_RED <=0;`
250			`oLED_GREEN <=0;`
251			`f_LED <=0;`
252			`end`
253			`else`
254			`begin`
255			`if(iRXD_Ready && (Pre_Target == LED) )`
256			`f_LED<=1;`
257			`if(f_LED)`
258			`begin`
259			`if( (CMD_Action == WRITE) && (CMD_MODE == DISPLAY) )`
260			`begin`
261			`oLED_RED <=CMD_ADDR;`
262			`oLED_GREEN <=CMD_DATA;`
263			`end`
264			`f_LED<=0;`
265			`end`
266			`end`
267			`end`
268			`/////////////////////////////////////////////////////////`
269			`//////////////// 7-SEG Control /////////////////////`
270			`always@(posedge iCLK or negedge iRST_n)`
271			`begin`
272			`if(!iRST_n)`
273			`begin`
274			`oSEG7_DIG<=0;`
275			`f_SEG7<=0;`
276			`end`
277			`else`
278			`begin`
279			`if(iRXD_Ready && (Pre_Target == SEG7) )`
280			`f_SEG7<=1;`
281			`if(f_SEG7)`
282			`begin`
283			`if( (CMD_Action == WRITE) && (CMD_MODE == DISPLAY) )`
284			`oSEG7_DIG<={CMD_ADDR[15:0],CMD_DATA};`
285			`f_SEG7<=0;`
286			`end`
287			`end`
288			`end`
289			`/////////////////////////////////////////////////////////`
290			`//////////////// Flash Control /////////////////////`
291			`always@(posedge iCLK or negedge iRST_n)`
292			`begin`
293			`if(!iRST_n)`
294			`begin`
295			`oFL_TXD_Start <=0;`
296			`oFL_Start <=0;`
297			`f_FLASH <=0;`
298			`mFL_ST <=0;`
299			`end`
300			`else`
301			`begin`
302			`if( CMD_Action == READ )`
303			`oFL_CMD <= CMD_READ;`
304			`else if( CMD_Action == WRITE )`
305			`oFL_CMD <= CMD_WRITE;`
306			`else if( CMD_Action == ERASE )`
307			`oFL_CMD <= CMD_CHP_ERA;`
308			`else`
309			`oFL_CMD <= 3'b000;`
310
311			`if(iRXD_Ready && (Pre_Target == FLASH))`
312			`f_FLASH<=1;`
313			`if(f_FLASH)`
314			`begin`
315			`case(mFL_ST)`
316			`0: begin`
317			`if( (CMD_MODE == NORMAL) && (CMD_Target == FLASH) && (CMD_DATA[15:8] == 8'hFF) )`
318			`begin`
319			`oFL_ADDR <= CMD_ADDR;`
320			`oFL_DATA <= CMD_DATA;`
321			`oFL_Start<= 1;`
322			`mFL_ST <= 1;`
323			`end`
324			`else`
325			`begin`
326			`mFL_ST <= 0;`
327			`f_FLASH <= 0;`
328			`end`
329			`end`
330			`1: begin`
331			`if(iFL_Ready)`
332			`begin`
333			`mFL_ST<=2;`
334			`oFL_Start<=0;`
335			`end`
336			`end`
337			`2: begin`
338			`oFL_Start<=1;`
339			`mFL_ST<=3;`
340			`end`
341			`3: begin`
342			`if(iFL_Ready)`
343			`begin`
344			`mFL_ST<=4;`
345			`oFL_Start<=0;`
346			`end`
347			`end`
348			`4: begin`
349			`oFL_Start<=1;`
350			`mFL_ST<=5;`
351			`end`
352			`5: begin`
353			`if(iFL_Ready)`
354			`begin`
355			`if( (oFL_CMD == CMD_READ) )`
356			`mFL_ST <= 6;`
357			`else`
358			`begin`
359			`mFL_ST <= 0;`
360			`f_FLASH <= 0;`
361			`end`
362			`oFL_Start <= 0;`
363			`end`
364			`end`
365			`6: begin`
366			`oFL_TXD_DATA <= iFL_DATA;`
367			`oFL_TXD_Start <= 1;`
368			`mFL_ST <= 7;`
369			`end`
370			`7: begin`
371			`if(iTXD_Done)`
372			`begin`
373			`oFL_TXD_Start<=0;`
374			`mFL_ST <= 0;`
375			`f_FLASH <= 0;`
376			`end`
377			`end`
378			`endcase`
379			`end`
380			`end`
381			`end`
382			`/////////////////////////////////////////////////////////`
383			`///////////////// PS2 Control /////////////////////`
384			`always@(posedge iCLK or negedge iRST_n)`
385			`begin`
386			`if(!iRST_n)`
387			`begin`
388			`oPS2_TXD_Start<=0;`
389			`f_PS2<=0;`
390			`mPS2_ST<=0;`
391			`end`
392			`else`
393			`begin`
394			`if(iPS2_Ready && iPS2_ScanCode!=8'h2e)`
395			`begin`
396			`f_PS2<=1;`
397			`oPS2_TXD_DATA<=iPS2_ScanCode;`
398			`end`
399			`if(f_PS2)`
400			`begin`
401			`case(mPS2_ST)`
402			`0: begin`
403			`oPS2_TXD_Start <=1;`
404			`mPS2_ST <=1;`
405			`end`
406			`1: begin`
407			`if(iTXD_Done)`
408			`begin`
409			`oPS2_TXD_Start <=0;`
410			`mPS2_ST <=0;`
411			`f_PS2 <=0;`
412			`end`
413			`end`
414			`endcase`
415			`end`
416			`end`
417			`end`
418			`/////////////////////////////////////////////////////////`
419			`//////////////// Sdram Control /////////////////////`
420			`always@(posedge iCLK or negedge iRST_n)`
421			`begin`
422			`if(!iRST_n)`
423			`begin`
424			`oSDR_TXD_Start <=0;`
425			`mSDR_WRn <=0;`
426			`mSDR_Start <=0;`
427			`f_SDRAM <=0;`
428			`mSDR_ST <=0;`
429			`end`
430			`else`
431			`begin`
432			`if( CMD_Action == READ )`
433			`mSDR_WRn <= 1'b0;`
434			`else if( CMD_Action == WRITE )`
435			`mSDR_WRn <= 1'b1;`
436
437			`if(iRXD_Ready && (Pre_Target == SDRAM))`
438			`f_SDRAM<=1;`
439			`if(f_SDRAM)`
440			`begin`
441			`case(mSDR_ST)`
442			`0: begin`
443			`if( (CMD_MODE == NORMAL) && (CMD_Target == SDRAM) )`
444			`begin`
445			`oSDR_ADDR <= CMD_ADDR;`
446			`oSDR_DATA <= CMD_DATA;`
447			`mSDR_Start <= 1;`
448			`mSDR_ST <= 1;`
449			`end`
450			`else`
451			`begin`
452			`mSDR_ST <= 0;`
453			`f_SDRAM <= 0;`
454			`end`
455			`end`
456			`1: begin`
457			`if(iSDR_Done)`
458			`begin`
459			`if(mSDR_WRn == 1'b0)`
460			`mSDR_ST <= 2;`
461			`else`
462			`begin`
463			`mSDR_ST <= 0;`
464			`f_SDRAM <= 0;`
465			`mSDR_Start <= 0;`
466			`end`
467			`end`
468			`end`
469			`2: begin`
470			`oSDR_TXD_DATA <= iSDR_DATA[7:0];`
471			`oSDR_TXD_Start <= 1;`
472			`mSDR_ST <= 3;`
473			`end`
474			`3: begin`
475			`if(iTXD_Done)`
476			`begin`
477			`oSDR_TXD_Start<=0;`
478			`mSDR_ST <= 4;`
479			`end`
480			`end`
481			`4: begin`
482			`oSDR_TXD_DATA <= iSDR_DATA[15:8];`
483			`oSDR_TXD_Start <= 1;`
484			`mSDR_ST <= 5;`
485			`end`
486			`5: begin`
487			`if(iTXD_Done)`
488			`begin`
489			`mSDR_Start <= 0;`
490			`oSDR_TXD_Start<=0;`
491			`mSDR_ST <= 0;`
492			`f_SDRAM <= 0;`
493			`end`
494			`end`
495			`endcase`
496			`end`
497			`end`
498			`end`
499
500			`assign oSDR_WR = mSDR_WRn & mSDR_Start;`
501			`assign oSDR_RD = ~mSDR_WRn & mSDR_Start;`
502			`/////////////////////////////////////////////////////////`
503			`//////////////// SRAM Control /////////////////////`
504			`always@(posedge iCLK or negedge iRST_n)`
505			`begin`
506			`if(!iRST_n)`
507			`begin`
508			`oSR_TXD_Start <=0;`
509			`mSR_WRn <=0;`
510			`mSR_Start <=0;`
511			`f_SRAM <=0;`
512			`mSR_ST <=0;`
513			`end`
514			`else`
515			`begin`
516			`if( CMD_Action == READ )`
517			`mSR_WRn <= 1'b0;`
518			`else if( CMD_Action == WRITE )`
519			`mSR_WRn <= 1'b1;`
520
521			`if(iRXD_Ready && (Pre_Target == SRAM))`
522			`f_SRAM<=1;`
523			`if(f_SRAM)`
524			`begin`
525			`case(mSR_ST)`
526			`0: begin`
527			`if( (CMD_MODE == NORMAL) && (CMD_Target == SRAM) )`
528			`begin`
529			`oSR_ADDR <= CMD_ADDR;`
530			`oSR_DATA <= CMD_DATA;`
531			`mSR_Start <= 1;`
532			`mSR_ST <= 1;`
533			`end`
534			`else`
535			`begin`
536			`mSR_ST <= 0;`
537			`f_SRAM <= 0;`
538			`end`
539			`end`
540			`1: begin`
541			`if(mSR_WRn == 1'b0)`
542			`mSR_ST <= 2;`
543			`else`
544			`begin`
545			`mSR_ST <= 0;`
546			`f_SRAM <= 0;`
547			`mSR_Start <= 0;`
548			`end`
549			`end`
550			`2: begin`
551			`oSR_TXD_DATA <= iSR_DATA[7:0];`
552			`oSR_TXD_Start <= 1;`
553			`mSR_ST <= 3;`
554			`end`
555			`3: begin`
556			`if(iTXD_Done)`
557			`begin`
558			`oSR_TXD_Start<=0;`
559			`mSR_ST <= 4;`
560			`end`
561			`end`
562			`4: begin`
563			`oSR_TXD_DATA <= iSR_DATA[15:8];`
564			`oSR_TXD_Start <= 1;`
565			`mSR_ST <= 5;`
566			`end`
567			`5: begin`
568			`if(iTXD_Done)`
569			`begin`
570			`mSR_Start <= 0;`
571			`oSR_TXD_Start<= 0;`
572			`mSR_ST <= 0;`
573			`f_SRAM <= 0;`
574			`end`
575			`end`
576			`endcase`
577			`end`
578			`end`
579			`end`
580
581			`assign oSR_OE_N = ~(~mSR_WRn & mSR_Start );`
582			`assign oSR_WE_N = ~( mSR_WRn & mSR_Start );`
583
584			`/////////////////////////////////////////////////////////`
585			`//////////////////// VGA Control /////////////////////`
586			`always@(posedge iCLK or negedge iRST_n)`
587			`begin`
588			`if(!iRST_n)`
589			`begin`
590			`oCursor_X <= 0;`
591			`oCursor_Y <= 0;`
592			`oCursor_R <= 0;`
593			`oCursor_G <= 0;`
594			`oCursor_B <= 0;`
595			`oOSD_CUR_EN <= 0;`
596			`f_VGA <= 0;`
597			`end`
598			`else`
599			`begin`
600			`if(iRXD_Ready && (Pre_Target == VGA) )`
601			`f_VGA<=1;`
602			`if(f_VGA)`
603			`begin`
604			`if( (CMD_Action == WRITE) && (CMD_MODE == DISPLAY) )`
605			`begin`
606			`case(CMD_ADDR[2:0])`
607			`0: oOSD_CUR_EN <= CMD_DATA[1:0];`
608			`1: oCursor_X <= CMD_DATA[9:0];`
609			`2: oCursor_Y <= CMD_DATA[9:0];`
610			`3: oCursor_R <= CMD_DATA[9:0];`
611			`4: oCursor_G <= CMD_DATA[9:0];`
612			`5: oCursor_B <= CMD_DATA[9:0];`
613			`endcase`
614			`end`
615			`f_VGA<=0;`
616			`end`
617			`end`
618			`end`
619			`/////////////////////////////////////////////////////////`
620
621			`endmodule`