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tylerapohl |
//Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
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//use of Altera Corporation's design tools, logic functions and other
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//software and tools, and its AMPP partner logic functions, and any
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//output files any of the foregoing (including device programming or
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//simulation files), and any associated documentation or information are
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//expressly subject to the terms and conditions of the Altera Program
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//License Subscription Agreement or other applicable license agreement,
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//including, without limitation, that your use is for the sole purpose
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//of programming logic devices manufactured by Altera and sold by Altera
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//or its authorized distributors. Please refer to the applicable
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//agreement for further details.
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module Multi_Flash( // Host Side
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oHS_DATA,iHS_DATA,iHS_ADDR,iHS_CMD,oHS_Ready,iHS_Start,
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// Async Side 1
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oAS1_DATA,iAS1_ADDR,
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// Async Side 2
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oAS2_DATA,iAS2_ADDR,
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// Async Side 3
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oAS3_DATA,iAS3_ADDR,
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// Control Signals
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iSelect,iCLK,iRST_n,
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// Flash Interface
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FL_DQ,FL_ADDR,FL_WE_n,FL_CE_n,FL_OE_n,FL_RST_n);
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// Host Side
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input [21:0] iHS_ADDR;
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input [7:0] iHS_DATA;
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input [2:0] iHS_CMD;
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input iHS_Start;
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output [7:0] oHS_DATA;
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output oHS_Ready;
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// Async Side 1
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input [21:0] iAS1_ADDR;
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output [7:0] oAS1_DATA;
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// Async Side 2
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input [21:0] iAS2_ADDR;
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output [7:0] oAS2_DATA;
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// Async Side 3
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input [21:0] iAS3_ADDR;
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output [7:0] oAS3_DATA;
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// Control Signals
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input [1:0] iSelect;
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input iCLK;
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input iRST_n;
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// Flash Interface
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output [21:0] FL_ADDR;
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inout [7:0] FL_DQ;
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output FL_OE_n;
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output FL_CE_n;
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output FL_WE_n;
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output FL_RST_n;
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// Internal Flash Link
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wire [7:0] mM2C_FL_DATA;
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wire [7:0] mC2M_FL_DATA;
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wire mFL_Ready;
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wire [21:0] mFL_ADDR;
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wire [2:0] mFL_CMD;
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wire mFL_Start;
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Flash_Multiplexer u0 ( // Host Side
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oHS_DATA,iHS_DATA,iHS_ADDR,iHS_CMD,oHS_Ready,iHS_Start,
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// Async Side 1
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oAS1_DATA,iAS1_ADDR,
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// Async Side 2
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oAS2_DATA,iAS2_ADDR,
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// Async Side 3
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oAS3_DATA,iAS3_ADDR,
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// Flash Side
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mM2C_FL_DATA,mC2M_FL_DATA,mFL_ADDR,mFL_CMD,mFL_Ready,mFL_Start,
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// Control Signals
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iSelect,iCLK,iRST_n);
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Flash_Controller u1 ( // Control Interface
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mC2M_FL_DATA,mM2C_FL_DATA,mFL_ADDR,mFL_CMD,
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mFL_Ready,mFL_Start,iCLK,iRST_n,
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// Flash Interface
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FL_DQ,FL_ADDR,FL_WE_n,FL_CE_n,FL_OE_n,FL_RST_n);
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endmodule
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