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//Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your

//use of Altera Corporation's design tools, logic functions and other

//software and tools, and its AMPP partner logic functions, and any

//output files any of the foregoing (including device programming or

//simulation files), and any associated documentation or information are

//expressly subject to the terms and conditions of the Altera Program

//License Subscription Agreement or other applicable license agreement,

//including, without limitation, that your use is for the sole purpose

//of programming logic devices manufactured by Altera and sold by Altera

//or its authorized distributors.  Please refer to the applicable

//agreement for further details.

`define ROWSTART        8

`define ROWSIZE         12

`define COLSTART        0

`define COLSIZE         8

`define BANKSTART       20

`define BANKSIZE        2

// Address and Data Bus Sizes

`define  ASIZE           23      // total address width of the SDRAM

`define  DSIZE           16      // Width of data bus to SDRAMS

//parameter     INIT_PER        =       100;            //      For Simulation

//      Controller Parameter

////////////    133 MHz ///////////////

/*

parameter       INIT_PER        =       32000;

parameter       REF_PER         =       1536;

parameter       SC_CL           =       3;

parameter       SC_RCD          =       3;

parameter       SC_RRD          =       7;

parameter       SC_PM           =       1;

parameter       SC_BL           =       1;

*/

///////////////////////////////////////

////////////    100 MHz ///////////////

/*

parameter       INIT_PER        =       24000;

parameter       REF_PER         =       1024;

parameter       SC_CL           =       3;

parameter       SC_RCD          =       3;

parameter       SC_RRD          =       7;

parameter       SC_PM           =       1;

parameter       SC_BL           =       1;

*/

///////////////////////////////////////

////////////    50 MHz  ///////////////

parameter       INIT_PER        =       12000;

parameter       REF_PER         =       512;

parameter       SC_CL           =       3;

parameter       SC_RCD          =       3;

parameter       SC_RRD          =       7;

parameter       SC_PM           =       1;

parameter       SC_BL           =       1;

///////////////////////////////////////

//      SDRAM Parameter

parameter       SDR_BL          =       (SC_PM == 1)?   3'b111  :

                                                        (SC_BL == 1)?   3'b000  :

                                                        (SC_BL == 2)?   3'b001  :

                                                        (SC_BL == 4)?   3'b010  :

                                                                                        3'b011  ;

parameter       SDR_BT          =       1'b0;   //      Sequential

                                                        //      1'b1:   //      Interteave

parameter       SDR_CL          =       (SC_CL == 2)?   3'b10:

                                                                                        3'b11;