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[/] [z80control/] [trunk/] [CII_Starter_USB_API_v1/] [HW/] [Multi_Sdram/] [command.v] - Blame information for rev 12

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//Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors.  Please refer to the applicable
//agreement for further details.
 
module command(
        CLK,
        RESET_N,
        SADDR,
        NOP,
        READA,
        WRITEA,
        REFRESH,
        PRECHARGE,
        LOAD_MODE,
        REF_REQ,
                INIT_REQ,
                PM_STOP,
                PM_DONE,
        REF_ACK,
        CM_ACK,
        OE,
        SA,
        BA,
        CS_N,
        CKE,
        RAS_N,
        CAS_N,
        WE_N
        );
 
`include        "Sdram_Params.h"
 
input                           CLK;                    // System Clock
input                           RESET_N;                // System Reset
input   [`ASIZE-1:0]            SADDR;                  // Address
input                           NOP;                    // Decoded NOP command
input                           READA;                  // Decoded READA command
input                           WRITEA;                 // Decoded WRITEA command
input                           REFRESH;                // Decoded REFRESH command
input                           PRECHARGE;              // Decoded PRECHARGE command
input                           LOAD_MODE;              // Decoded LOAD_MODE command
input                           REF_REQ;                // Hidden refresh request
input                                                   INIT_REQ;                               // Hidden initial request
input                                                   PM_STOP;                                // Page mode stop
input                                                   PM_DONE;                                // Page mode done
output                          REF_ACK;                // Refresh request acknowledge
output                          CM_ACK;                 // Command acknowledge
output                          OE;                     // OE signal for data path module
output  [11:0]                  SA;                     // SDRAM address
output  [1:0]                   BA;                     // SDRAM bank address
output  [1:0]                   CS_N;                   // SDRAM chip selects
output                          CKE;                    // SDRAM clock enable
output                          RAS_N;                  // SDRAM RAS
output                          CAS_N;                  // SDRAM CAS
output                          WE_N;                   // SDRAM WE_N
 
 
reg                             CM_ACK;
reg                             REF_ACK;
reg                             OE;
reg     [11:0]                  SA;
reg     [1:0]                   BA;
reg     [1:0]                   CS_N;
reg                             CKE;
reg                             RAS_N;
reg                             CAS_N;
reg                             WE_N;
 
 
 
// Internal signals
reg                             do_reada;
reg                             do_writea;
reg                             do_refresh;
reg                             do_precharge;
reg                             do_load_mode;
reg                                                             do_initial;
reg                             command_done;
reg     [7:0]                   command_delay;
reg     [1:0]                   rw_shift;
reg                             do_act;
reg                             rw_flag;
reg                             do_rw;
reg     [6:0]                   oe_shift;
reg                             oe1;
reg                             oe2;
reg                             oe3;
reg                             oe4;
reg     [3:0]                   rp_shift;
reg                             rp_done;
reg                                                             ex_read;
reg                                                             ex_write;
 
wire    [`ROWSIZE - 1:0]        rowaddr;
wire    [`COLSIZE - 1:0]        coladdr;
wire    [`BANKSIZE - 1:0]       bankaddr;
 
assign   rowaddr   = SADDR[`ROWSTART + `ROWSIZE - 1: `ROWSTART];          // assignment of the row address bits from SADDR
assign   coladdr   = SADDR[`COLSTART + `COLSIZE - 1:`COLSTART];           // assignment of the column address bits
assign   bankaddr  = SADDR[`BANKSTART + `BANKSIZE - 1:`BANKSTART];        // assignment of the bank address bits
 
 
 
// This always block monitors the individual command lines and issues a command
// to the next stage if there currently another command already running.
//
always @(posedge CLK or negedge RESET_N)
begin
        if (RESET_N == 0)
        begin
                do_reada        <= 0;
                do_writea       <= 0;
                do_refresh      <= 0;
                do_precharge    <= 0;
                do_load_mode    <= 0;
                                do_initial              <= 0;
                command_done    <= 0;
                command_delay   <= 0;
                rw_flag         <= 0;
                rp_shift        <= 0;
                rp_done         <= 0;
                                ex_read                 <= 0;
                                ex_write                <= 0;
        end
 
        else
        begin
 
//  Issue the appropriate command if the sdram is not currently busy
                        if( INIT_REQ == 1 )
                        begin
                do_reada        <= 0;
                do_writea       <= 0;
                do_refresh      <= 0;
                do_precharge    <= 0;
                do_load_mode    <= 0;
                                do_initial              <= 1;
                command_done    <= 0;
                command_delay   <= 0;
                rw_flag         <= 0;
                rp_shift        <= 0;
                rp_done         <= 0;
                                ex_read                 <= 0;
                                ex_write                <= 0;
                        end
                        else
                        begin
                                do_initial              <= 0;
 
                if ((REF_REQ == 1 | REFRESH == 1) & command_done == 0 & do_refresh == 0 & rp_done == 0         // Refresh
                        & do_reada == 0 & do_writea == 0)
                        do_refresh <= 1;
                else
                        do_refresh <= 0;
 
                if ((READA == 1) & (command_done == 0) & (do_reada == 0) & (rp_done == 0) & (REF_REQ == 0))    // READA
                begin
                                        do_reada <= 1;
                                                ex_read <= 1;
                                end
                else
                        do_reada <= 0;
 
                if ((WRITEA == 1) & (command_done == 0) & (do_writea == 0) & (rp_done == 0) & (REF_REQ == 0))  // WRITEA
                begin
                                        do_writea <= 1;
                                                ex_write <= 1;
                                end
                else
                        do_writea <= 0;
 
                if ((PRECHARGE == 1) & (command_done == 0) & (do_precharge == 0))                              // PRECHARGE
                        do_precharge <= 1;
                else
                        do_precharge <= 0;
 
                if ((LOAD_MODE == 1) & (command_done == 0) & (do_load_mode == 0))                              // LOADMODE
                        do_load_mode <= 1;
                else
                        do_load_mode <= 0;
 
// set command_delay shift register and command_done flag
// The command delay shift register is a timer that is used to ensure that
// the SDRAM devices have had sufficient time to finish the last command.
 
                if ((do_refresh == 1) | (do_reada == 1) | (do_writea == 1) | (do_precharge == 1)
                     | (do_load_mode == 1))
                begin
                        command_delay <= 8'b11111111;
                        command_done  <= 1;
                        rw_flag <= do_reada;
                end
 
                else
                begin
                        command_done        <= command_delay[0];                // the command_delay shift operation
                        command_delay           <= (command_delay>>1);
                end
 
 
 // start additional timer that is used for the refresh, writea, reada commands               
                if (command_delay[0] == 0 & command_done == 1)
                begin
                        rp_shift <= 4'b1111;
                        rp_done <= 1;
                end
                else
                begin
                                        if(SC_PM == 0)
                                        begin
                                                rp_shift        <= (rp_shift>>1);
                        rp_done         <= rp_shift[0];
                                        end
                                        else
                                        begin
                                                if( (ex_read == 0) && (ex_write == 0) )
                                                begin
                                                        rp_shift        <= (rp_shift>>1);
                                rp_done         <= rp_shift[0];
                                                end
                                                else
                                                begin
                                                        if( PM_STOP==1 )
                                                        begin
                                                                rp_shift        <= (rp_shift>>1);
                                        rp_done     <= rp_shift[0];
                                                                ex_read         <= 1'b0;
                                                                ex_write        <= 1'b0;
                                                        end
                                                end
                                        end
                end
                        end
        end
end
 
 
// logic that generates the OE signal for the data path module
// For normal burst write he duration of OE is dependent on the configured burst length.
// For page mode accesses(SC_PM=1) the OE signal is turned on at the start of the write command
// and is left on until a PRECHARGE(page burst terminate) is detected.
//
always @(posedge CLK or negedge RESET_N)
begin
        if (RESET_N == 0)
        begin
                oe_shift <= 0;
                oe1      <= 0;
                oe2      <= 0;
                OE       <= 0;
        end
        else
        begin
                if (SC_PM == 0)
                begin
                        if (do_writea == 1)
                        begin
                                if (SC_BL == 1)                       //  Set the shift register to the appropriate
                                        oe_shift <= 0;                // value based on burst length.
                                else if (SC_BL == 2)
                                        oe_shift <= 1;
                                else if (SC_BL == 4)
                                        oe_shift <= 7;
                                else if (SC_BL == 8)
                                        oe_shift <= 127;
                                oe1 <= 1;
                        end
                        else
                        begin
                                oe_shift <= (oe_shift>>1);
                                oe1  <= oe_shift[0];
                                oe2  <= oe1;
                                oe3  <= oe2;
                                oe4  <= oe3;
                                if (SC_RCD == 2)
                                        OE <= oe3;
                                else
                                        OE <= oe4;
                        end
                end
                else
                begin
                        if (do_writea == 1)                                    // OE generation for page mode accesses
                                oe4   <= 1;
                        else if (do_precharge == 1 | do_reada == 1 | do_refresh==1 | do_initial == 1 | PM_STOP==1 )
                                oe4   <= 0;
                        OE <= oe4;
                end
 
        end
end
 
 
 
 
// This always block tracks the time between the activate command and the
// subsequent WRITEA or READA command, RC.  The shift register is set using
// the configuration register setting SC_RCD. The shift register is loaded with
// a single '1' with the position within the register dependent on SC_RCD.
// When the '1' is shifted out of the register it sets so_rw which triggers
// a writea or reada command
//
always @(posedge CLK or negedge RESET_N)
begin
        if (RESET_N == 0)
        begin
                rw_shift <= 0;
                do_rw    <= 0;
        end
 
        else
        begin
 
                if ((do_reada == 1) | (do_writea == 1))
                begin
                        if (SC_RCD == 1)                          // Set the shift register
                                do_rw <= 1;
                        else if (SC_RCD == 2)
                                rw_shift <= 1;
                        else if (SC_RCD == 3)
                                rw_shift <= 2;
                end
                else
                begin
                        rw_shift <= (rw_shift>>1);
                        do_rw    <= rw_shift[0];
                end
        end
end
 
// This always block generates the command acknowledge, CM_ACK, signal.
// It also generates the acknowledge signal, REF_ACK, that acknowledges
// a refresh request that was generated by the internal refresh timer circuit.
always @(posedge CLK or negedge RESET_N)
begin
 
        if (RESET_N == 0)
        begin
                CM_ACK   <= 0;
                REF_ACK  <= 0;
        end
 
        else
        begin
                if (do_refresh == 1 & REF_REQ == 1)                   // Internal refresh timer refresh request
                        REF_ACK <= 1;
                else if ((do_refresh == 1) | (do_reada == 1) | (do_writea == 1) | (do_precharge == 1)   // externa  commands
                         | (do_load_mode))
                        CM_ACK <= 1;
                else
                begin
                        REF_ACK <= 0;
                        CM_ACK  <= 0;
                end
        end
end
 
 
 
 
 
 
 
// This always block generates the address, cs, cke, and command signals(ras,cas,wen)
// 
always @(posedge CLK ) begin
        if (RESET_N==0) begin
                SA    <= 0;
                BA    <= 0;
                CS_N  <= 1;
                RAS_N <= 1;
                CAS_N <= 1;
                WE_N  <= 1;
                CKE   <= 0;
        end
        else begin
                CKE <= 1;
 
// Generate SA  
                if (do_writea == 1 | do_reada == 1)    // ACTIVATE command is being issued, so present the row address
                        SA <= rowaddr;
                else
                        SA <= coladdr;                 // else alway present column address
                if ((do_rw==1) | (do_precharge))
                        SA[10] <= !SC_PM;              // set SA[10] for autoprecharge read/write or for a precharge all command
                                                       // don't set it if the controller is in page mode.           
                if (do_precharge==1 | do_load_mode==1)
                        BA <= 0;                       // Set BA=0 if performing a precharge or load_mode command
                else
                        BA <= bankaddr[1:0];           // else set it with the appropriate address bits
 
                if (do_refresh==1 | do_precharge==1 | do_load_mode==1 | do_initial==1)
                        CS_N <= 0;                                    // Select both chip selects if performing
                else                                                  // refresh, precharge(all) or load_mode
                begin
                        CS_N[0] <= SADDR[`ASIZE-1];                   // else set the chip selects based off of the
                        CS_N[1] <= ~SADDR[`ASIZE-1];                  // msb address bit
                end
 
                                if(do_load_mode==1)
                                SA        <= {2'b00,SDR_CL,SDR_BT,SDR_BL};
 
 
//Generate the appropriate logic levels on RAS_N, CAS_N, and WE_N
//depending on the issued command.
//              
                if ( do_refresh==1 ) begin                        // Refresh: S=00, RAS=0, CAS=0, WE=1
                        RAS_N <= 0;
                        CAS_N <= 0;
                        WE_N  <= 1;
                end
                else if ((do_precharge==1) & ((oe4 == 1) | (rw_flag == 1))) begin      // burst terminate if write is active
                        RAS_N <= 1;
                        CAS_N <= 1;
                        WE_N  <= 0;
                end
                else if (do_precharge==1) begin                 // Precharge All: S=00, RAS=0, CAS=1, WE=0
                        RAS_N <= 0;
                        CAS_N <= 1;
                        WE_N  <= 0;
                end
                else if (do_load_mode==1) begin                 // Mode Write: S=00, RAS=0, CAS=0, WE=0
                        RAS_N <= 0;
                        CAS_N <= 0;
                        WE_N  <= 0;
                end
                else if (do_reada == 1 | do_writea == 1) begin  // Activate: S=01 or 10, RAS=0, CAS=1, WE=1
                        RAS_N <= 0;
                        CAS_N <= 1;
                        WE_N  <= 1;
                end
                else if (do_rw == 1) begin                      // Read/Write: S=01 or 10, RAS=1, CAS=0, WE=0 or 1
                        RAS_N <= 1;
                        CAS_N <= 0;
                        WE_N  <= rw_flag;
                end
                                else if (do_initial ==1) begin
                        RAS_N <= 1;
                        CAS_N <= 1;
                        WE_N  <= 1;
                                end
                else begin                                      // No Operation: RAS=1, CAS=1, WE=1
                        RAS_N <= 1;
                        CAS_N <= 1;
                        WE_N  <= 1;
                end
        end
end
 
endmodule

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[/] [z80control/] [trunk/] [CII_Starter_USB_API_v1/] [HW/] [Multi_Sdram/] [command.v] - Blame information for rev 12

Line No.	Rev	Author	Line
1	12	tylerapohl	`//Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your`
2			`//use of Altera Corporation's design tools, logic functions and other`
3			`//software and tools, and its AMPP partner logic functions, and any`
4			`//output files any of the foregoing (including device programming or`
5			`//simulation files), and any associated documentation or information are`
6			`//expressly subject to the terms and conditions of the Altera Program`
7			`//License Subscription Agreement or other applicable license agreement,`
8			`//including, without limitation, that your use is for the sole purpose`
9			`//of programming logic devices manufactured by Altera and sold by Altera`
10			`//or its authorized distributors. Please refer to the applicable`
11			`//agreement for further details.`
12
13			`module command(`
14			`CLK,`
15			`RESET_N,`
16			`SADDR,`
17			`NOP,`
18			`READA,`
19			`WRITEA,`
20			`REFRESH,`
21			`PRECHARGE,`
22			`LOAD_MODE,`
23			`REF_REQ,`
24			`INIT_REQ,`
25			`PM_STOP,`
26			`PM_DONE,`
27			`REF_ACK,`
28			`CM_ACK,`
29			`OE,`
30			`SA,`
31			`BA,`
32			`CS_N,`
33			`CKE,`
34			`RAS_N,`
35			`CAS_N,`
36			`WE_N`
37			`);`
38
39			`include "Sdram_Params.h"
40
41			`input CLK; // System Clock`
42			`input RESET_N; // System Reset`
43			input [`ASIZE-1:0] SADDR; // Address
44			`input NOP; // Decoded NOP command`
45			`input READA; // Decoded READA command`
46			`input WRITEA; // Decoded WRITEA command`
47			`input REFRESH; // Decoded REFRESH command`
48			`input PRECHARGE; // Decoded PRECHARGE command`
49			`input LOAD_MODE; // Decoded LOAD_MODE command`
50			`input REF_REQ; // Hidden refresh request`
51			`input INIT_REQ; // Hidden initial request`
52			`input PM_STOP; // Page mode stop`
53			`input PM_DONE; // Page mode done`
54			`output REF_ACK; // Refresh request acknowledge`
55			`output CM_ACK; // Command acknowledge`
56			`output OE; // OE signal for data path module`
57			`output [11:0] SA; // SDRAM address`
58			`output [1:0] BA; // SDRAM bank address`
59			`output [1:0] CS_N; // SDRAM chip selects`
60			`output CKE; // SDRAM clock enable`
61			`output RAS_N; // SDRAM RAS`
62			`output CAS_N; // SDRAM CAS`
63			`output WE_N; // SDRAM WE_N`
64
65
66			`reg CM_ACK;`
67			`reg REF_ACK;`
68			`reg OE;`
69			`reg [11:0] SA;`
70			`reg [1:0] BA;`
71			`reg [1:0] CS_N;`
72			`reg CKE;`
73			`reg RAS_N;`
74			`reg CAS_N;`
75			`reg WE_N;`
76
77
78
79			`// Internal signals`
80			`reg do_reada;`
81			`reg do_writea;`
82			`reg do_refresh;`
83			`reg do_precharge;`
84			`reg do_load_mode;`
85			`reg do_initial;`
86			`reg command_done;`
87			`reg [7:0] command_delay;`
88			`reg [1:0] rw_shift;`
89			`reg do_act;`
90			`reg rw_flag;`
91			`reg do_rw;`
92			`reg [6:0] oe_shift;`
93			`reg oe1;`
94			`reg oe2;`
95			`reg oe3;`
96			`reg oe4;`
97			`reg [3:0] rp_shift;`
98			`reg rp_done;`
99			`reg ex_read;`
100			`reg ex_write;`
101
102			wire [`ROWSIZE - 1:0] rowaddr;
103			wire [`COLSIZE - 1:0] coladdr;
104			wire [`BANKSIZE - 1:0] bankaddr;
105
106			assign rowaddr = SADDR[`ROWSTART + `ROWSIZE - 1: `ROWSTART]; // assignment of the row address bits from SADDR
107			assign coladdr = SADDR[`COLSTART + `COLSIZE - 1:`COLSTART]; // assignment of the column address bits
108			assign bankaddr = SADDR[`BANKSTART + `BANKSIZE - 1:`BANKSTART]; // assignment of the bank address bits
109
110
111
112			`// This always block monitors the individual command lines and issues a command`
113			`// to the next stage if there currently another command already running.`
114			`//`
115			`always @(posedge CLK or negedge RESET_N)`
116			`begin`
117			`if (RESET_N == 0)`
118			`begin`
119			`do_reada <= 0;`
120			`do_writea <= 0;`
121			`do_refresh <= 0;`
122			`do_precharge <= 0;`
123			`do_load_mode <= 0;`
124			`do_initial <= 0;`
125			`command_done <= 0;`
126			`command_delay <= 0;`
127			`rw_flag <= 0;`
128			`rp_shift <= 0;`
129			`rp_done <= 0;`
130			`ex_read <= 0;`
131			`ex_write <= 0;`
132			`end`
133
134			`else`
135			`begin`
136
137			`// Issue the appropriate command if the sdram is not currently busy`
138			`if( INIT_REQ == 1 )`
139			`begin`
140			`do_reada <= 0;`
141			`do_writea <= 0;`
142			`do_refresh <= 0;`
143			`do_precharge <= 0;`
144			`do_load_mode <= 0;`
145			`do_initial <= 1;`
146			`command_done <= 0;`
147			`command_delay <= 0;`
148			`rw_flag <= 0;`
149			`rp_shift <= 0;`
150			`rp_done <= 0;`
151			`ex_read <= 0;`
152			`ex_write <= 0;`
153			`end`
154			`else`
155			`begin`
156			`do_initial <= 0;`
157
158			`if ((REF_REQ == 1 \| REFRESH == 1) & command_done == 0 & do_refresh == 0 & rp_done == 0 // Refresh`
159			`& do_reada == 0 & do_writea == 0)`
160			`do_refresh <= 1;`
161			`else`
162			`do_refresh <= 0;`
163
164			`if ((READA == 1) & (command_done == 0) & (do_reada == 0) & (rp_done == 0) & (REF_REQ == 0)) // READA`
165			`begin`
166			`do_reada <= 1;`
167			`ex_read <= 1;`
168			`end`
169			`else`
170			`do_reada <= 0;`
171
172			`if ((WRITEA == 1) & (command_done == 0) & (do_writea == 0) & (rp_done == 0) & (REF_REQ == 0)) // WRITEA`
173			`begin`
174			`do_writea <= 1;`
175			`ex_write <= 1;`
176			`end`
177			`else`
178			`do_writea <= 0;`
179
180			`if ((PRECHARGE == 1) & (command_done == 0) & (do_precharge == 0)) // PRECHARGE`
181			`do_precharge <= 1;`
182			`else`
183			`do_precharge <= 0;`
184
185			`if ((LOAD_MODE == 1) & (command_done == 0) & (do_load_mode == 0)) // LOADMODE`
186			`do_load_mode <= 1;`
187			`else`
188			`do_load_mode <= 0;`
189
190			`// set command_delay shift register and command_done flag`
191			`// The command delay shift register is a timer that is used to ensure that`
192			`// the SDRAM devices have had sufficient time to finish the last command.`
193
194			`if ((do_refresh == 1) \| (do_reada == 1) \| (do_writea == 1) \| (do_precharge == 1)`
195			`\| (do_load_mode == 1))`
196			`begin`
197			`command_delay <= 8'b11111111;`
198			`command_done <= 1;`
199			`rw_flag <= do_reada;`
200			`end`
201
202			`else`
203			`begin`
204			`command_done <= command_delay[0]; // the command_delay shift operation`
205			`command_delay <= (command_delay>>1);`
206			`end`
207
208
209			`// start additional timer that is used for the refresh, writea, reada commands`
210			`if (command_delay[0] == 0 & command_done == 1)`
211			`begin`
212			`rp_shift <= 4'b1111;`
213			`rp_done <= 1;`
214			`end`
215			`else`
216			`begin`
217			`if(SC_PM == 0)`
218			`begin`
219			`rp_shift <= (rp_shift>>1);`
220			`rp_done <= rp_shift[0];`
221			`end`
222			`else`
223			`begin`
224			`if( (ex_read == 0) && (ex_write == 0) )`
225			`begin`
226			`rp_shift <= (rp_shift>>1);`
227			`rp_done <= rp_shift[0];`
228			`end`
229			`else`
230			`begin`
231			`if( PM_STOP==1 )`
232			`begin`
233			`rp_shift <= (rp_shift>>1);`
234			`rp_done <= rp_shift[0];`
235			`ex_read <= 1'b0;`
236			`ex_write <= 1'b0;`
237			`end`
238			`end`
239			`end`
240			`end`
241			`end`
242			`end`
243			`end`
244
245
246			`// logic that generates the OE signal for the data path module`
247			`// For normal burst write he duration of OE is dependent on the configured burst length.`
248			`// For page mode accesses(SC_PM=1) the OE signal is turned on at the start of the write command`
249			`// and is left on until a PRECHARGE(page burst terminate) is detected.`
250			`//`
251			`always @(posedge CLK or negedge RESET_N)`
252			`begin`
253			`if (RESET_N == 0)`
254			`begin`
255			`oe_shift <= 0;`
256			`oe1 <= 0;`
257			`oe2 <= 0;`
258			`OE <= 0;`
259			`end`
260			`else`
261			`begin`
262			`if (SC_PM == 0)`
263			`begin`
264			`if (do_writea == 1)`
265			`begin`
266			`if (SC_BL == 1) // Set the shift register to the appropriate`
267			`oe_shift <= 0; // value based on burst length.`
268			`else if (SC_BL == 2)`
269			`oe_shift <= 1;`
270			`else if (SC_BL == 4)`
271			`oe_shift <= 7;`
272			`else if (SC_BL == 8)`
273			`oe_shift <= 127;`
274			`oe1 <= 1;`
275			`end`
276			`else`
277			`begin`
278			`oe_shift <= (oe_shift>>1);`
279			`oe1 <= oe_shift[0];`
280			`oe2 <= oe1;`
281			`oe3 <= oe2;`
282			`oe4 <= oe3;`
283			`if (SC_RCD == 2)`
284			`OE <= oe3;`
285			`else`
286			`OE <= oe4;`
287			`end`
288			`end`
289			`else`
290			`begin`
291			`if (do_writea == 1) // OE generation for page mode accesses`
292			`oe4 <= 1;`
293			`else if (do_precharge == 1 \| do_reada == 1 \| do_refresh==1 \| do_initial == 1 \| PM_STOP==1 )`
294			`oe4 <= 0;`
295			`OE <= oe4;`
296			`end`
297
298			`end`
299			`end`
300
301
302
303
304			`// This always block tracks the time between the activate command and the`
305			`// subsequent WRITEA or READA command, RC. The shift register is set using`
306			`// the configuration register setting SC_RCD. The shift register is loaded with`
307			`// a single '1' with the position within the register dependent on SC_RCD.`
308			`// When the '1' is shifted out of the register it sets so_rw which triggers`
309			`// a writea or reada command`
310			`//`
311			`always @(posedge CLK or negedge RESET_N)`
312			`begin`
313			`if (RESET_N == 0)`
314			`begin`
315			`rw_shift <= 0;`
316			`do_rw <= 0;`
317			`end`
318
319			`else`
320			`begin`
321
322			`if ((do_reada == 1) \| (do_writea == 1))`
323			`begin`
324			`if (SC_RCD == 1) // Set the shift register`
325			`do_rw <= 1;`
326			`else if (SC_RCD == 2)`
327			`rw_shift <= 1;`
328			`else if (SC_RCD == 3)`
329			`rw_shift <= 2;`
330			`end`
331			`else`
332			`begin`
333			`rw_shift <= (rw_shift>>1);`
334			`do_rw <= rw_shift[0];`
335			`end`
336			`end`
337			`end`
338
339			`// This always block generates the command acknowledge, CM_ACK, signal.`
340			`// It also generates the acknowledge signal, REF_ACK, that acknowledges`
341			`// a refresh request that was generated by the internal refresh timer circuit.`
342			`always @(posedge CLK or negedge RESET_N)`
343			`begin`
344
345			`if (RESET_N == 0)`
346			`begin`
347			`CM_ACK <= 0;`
348			`REF_ACK <= 0;`
349			`end`
350
351			`else`
352			`begin`
353			`if (do_refresh == 1 & REF_REQ == 1) // Internal refresh timer refresh request`
354			`REF_ACK <= 1;`
355			`else if ((do_refresh == 1) \| (do_reada == 1) \| (do_writea == 1) \| (do_precharge == 1) // externa commands`
356			`\| (do_load_mode))`
357			`CM_ACK <= 1;`
358			`else`
359			`begin`
360			`REF_ACK <= 0;`
361			`CM_ACK <= 0;`
362			`end`
363			`end`
364			`end`
365
366
367
368
369
370
371
372			`// This always block generates the address, cs, cke, and command signals(ras,cas,wen)`
373			`//`
374			`always @(posedge CLK ) begin`
375			`if (RESET_N==0) begin`
376			`SA <= 0;`
377			`BA <= 0;`
378			`CS_N <= 1;`
379			`RAS_N <= 1;`
380			`CAS_N <= 1;`
381			`WE_N <= 1;`
382			`CKE <= 0;`
383			`end`
384			`else begin`
385			`CKE <= 1;`
386
387			`// Generate SA`
388			`if (do_writea == 1 \| do_reada == 1) // ACTIVATE command is being issued, so present the row address`
389			`SA <= rowaddr;`
390			`else`
391			`SA <= coladdr; // else alway present column address`
392			`if ((do_rw==1) \| (do_precharge))`
393			`SA[10] <= !SC_PM; // set SA[10] for autoprecharge read/write or for a precharge all command`
394			`// don't set it if the controller is in page mode.`
395			`if (do_precharge==1 \| do_load_mode==1)`
396			`BA <= 0; // Set BA=0 if performing a precharge or load_mode command`
397			`else`
398			`BA <= bankaddr[1:0]; // else set it with the appropriate address bits`
399
400			`if (do_refresh==1 \| do_precharge==1 \| do_load_mode==1 \| do_initial==1)`
401			`CS_N <= 0; // Select both chip selects if performing`
402			`else // refresh, precharge(all) or load_mode`
403			`begin`
404			CS_N[0] <= SADDR[`ASIZE-1]; // else set the chip selects based off of the
405			CS_N[1] <= ~SADDR[`ASIZE-1]; // msb address bit
406			`end`
407
408			`if(do_load_mode==1)`
409			`SA <= {2'b00,SDR_CL,SDR_BT,SDR_BL};`
410
411
412			`//Generate the appropriate logic levels on RAS_N, CAS_N, and WE_N`
413			`//depending on the issued command.`
414			`//`
415			`if ( do_refresh==1 ) begin // Refresh: S=00, RAS=0, CAS=0, WE=1`
416			`RAS_N <= 0;`
417			`CAS_N <= 0;`
418			`WE_N <= 1;`
419			`end`
420			`else if ((do_precharge==1) & ((oe4 == 1) \| (rw_flag == 1))) begin // burst terminate if write is active`
421			`RAS_N <= 1;`
422			`CAS_N <= 1;`
423			`WE_N <= 0;`
424			`end`
425			`else if (do_precharge==1) begin // Precharge All: S=00, RAS=0, CAS=1, WE=0`
426			`RAS_N <= 0;`
427			`CAS_N <= 1;`
428			`WE_N <= 0;`
429			`end`
430			`else if (do_load_mode==1) begin // Mode Write: S=00, RAS=0, CAS=0, WE=0`
431			`RAS_N <= 0;`
432			`CAS_N <= 0;`
433			`WE_N <= 0;`
434			`end`
435			`else if (do_reada == 1 \| do_writea == 1) begin // Activate: S=01 or 10, RAS=0, CAS=1, WE=1`
436			`RAS_N <= 0;`
437			`CAS_N <= 1;`
438			`WE_N <= 1;`
439			`end`
440			`else if (do_rw == 1) begin // Read/Write: S=01 or 10, RAS=1, CAS=0, WE=0 or 1`
441			`RAS_N <= 1;`
442			`CAS_N <= 0;`
443			`WE_N <= rw_flag;`
444			`end`
445			`else if (do_initial ==1) begin`
446			`RAS_N <= 1;`
447			`CAS_N <= 1;`
448			`WE_N <= 1;`
449			`end`
450			`else begin // No Operation: RAS=1, CAS=1, WE=1`
451			`RAS_N <= 1;`
452			`CAS_N <= 1;`
453			`WE_N <= 1;`
454			`end`
455			`end`
456			`end`
457
458			`endmodule`