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[/] [z80control/] [trunk/] [CII_Starter_USB_API_v1/] [HW/] [VGA_Controller/] [VGA_Controller.v] - Blame information for rev 12

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//Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors.  Please refer to the applicable
//agreement for further details.
 
module  VGA_Controller( //      Host Side
                                                iCursor_RGB_EN,
                                                iCursor_X,
                                                iCursor_Y,
                                                iCursor_R,
                                                iCursor_G,
                                                iCursor_B,
                                                iRed,
                                                iGreen,
                                                iBlue,
                                                oAddress,
                                                oCoord_X,
                                                oCoord_Y,
                                                //      VGA Side
                                                oVGA_R,
                                                oVGA_G,
                                                oVGA_B,
                                                oVGA_H_SYNC,
                                                oVGA_V_SYNC,
                                                oVGA_SYNC,
                                                oVGA_BLANK,
                                                oVGA_CLOCK,
                                                //      Control Signal
                                                iCLK,
                                                iRST_N  );
 
`include "VGA_Param.h"
 
//      Host Side
output  reg     [19:0]   oAddress;
output  reg     [9:0]    oCoord_X;
output  reg     [9:0]    oCoord_Y;
input           [3:0]    iCursor_RGB_EN;
input           [9:0]    iCursor_X;
input           [9:0]    iCursor_Y;
input           [9:0]    iCursor_R;
input           [9:0]    iCursor_G;
input           [9:0]    iCursor_B;
input           [9:0]    iRed;
input           [9:0]    iGreen;
input           [9:0]    iBlue;
//      VGA Side
output          [9:0]    oVGA_R;
output          [9:0]    oVGA_G;
output          [9:0]    oVGA_B;
output  reg                     oVGA_H_SYNC;
output  reg                     oVGA_V_SYNC;
output                          oVGA_SYNC;
output                          oVGA_BLANK;
output                          oVGA_CLOCK;
//      Control Signal
input                           iCLK;
input                           iRST_N;
 
//      Internal Registers and Wires
reg             [9:0]            H_Cont;
reg             [9:0]            V_Cont;
reg             [9:0]            Cur_Color_R;
reg             [9:0]            Cur_Color_G;
reg             [9:0]            Cur_Color_B;
wire                            mCursor_EN;
wire                            mRed_EN;
wire                            mGreen_EN;
wire                            mBlue_EN;
 
assign  oVGA_BLANK      =       oVGA_H_SYNC & oVGA_V_SYNC;
assign  oVGA_SYNC       =       1'b0;
assign  oVGA_CLOCK      =       iCLK;
assign  mCursor_EN      =       iCursor_RGB_EN[3];
assign  mRed_EN         =       iCursor_RGB_EN[2];
assign  mGreen_EN       =       iCursor_RGB_EN[1];
assign  mBlue_EN        =       iCursor_RGB_EN[0];
 
assign  oVGA_R  =       (       H_Cont>=X_START+9       && H_Cont<X_START+H_SYNC_ACT+9 &&
                                                V_Cont>=Y_START         && V_Cont<Y_START+V_SYNC_ACT )
                                                ?       (mRed_EN        ?       Cur_Color_R     :       0)       :       0;
assign  oVGA_G  =       (       H_Cont>=X_START+9       && H_Cont<X_START+H_SYNC_ACT+9 &&
                                                V_Cont>=Y_START         && V_Cont<Y_START+V_SYNC_ACT )
                                                ?       (mGreen_EN      ?       Cur_Color_G     :       0)       :       0;
assign  oVGA_B  =       (       H_Cont>=X_START+9       && H_Cont<X_START+H_SYNC_ACT+9 &&
                                                V_Cont>=Y_START         && V_Cont<Y_START+V_SYNC_ACT )
                                                ?       (mBlue_EN       ?       Cur_Color_B     :       0)       :       0;
 
//      Pixel LUT Address Generator
always@(posedge iCLK or negedge iRST_N)
begin
        if(!iRST_N)
        begin
                oCoord_X        <=      0;
                oCoord_Y        <=      0;
                oAddress        <=      0;
        end
        else
        begin
                if(     H_Cont>=X_START && H_Cont<X_START+H_SYNC_ACT &&
                        V_Cont>=Y_START && V_Cont<Y_START+V_SYNC_ACT )
                begin
                        oCoord_X        <=      H_Cont-X_START;
                        oCoord_Y        <=      V_Cont-Y_START;
                        oAddress        <=      oCoord_Y*H_SYNC_ACT+oCoord_X-3;
                end
        end
end
 
//      Cursor Generator        
always@(posedge iCLK or negedge iRST_N)
begin
        if(!iRST_N)
        begin
                Cur_Color_R     <=      0;
                Cur_Color_G     <=      0;
                Cur_Color_B     <=      0;
        end
        else
        begin
                if(     H_Cont>=X_START+8 && H_Cont<X_START+H_SYNC_ACT+8 &&
                        V_Cont>=Y_START && V_Cont<Y_START+V_SYNC_ACT )
                begin
                        if( (   (H_Cont==X_START + 8 + iCursor_X)       ||
                                        (H_Cont==X_START + 8 + iCursor_X+1) ||
                                        (H_Cont==X_START + 8 + iCursor_X-1) ||
                                        (V_Cont==Y_START + iCursor_Y)   ||
                                        (V_Cont==Y_START + iCursor_Y+1) ||
                                        (V_Cont==Y_START + iCursor_Y-1) )
                                        && mCursor_EN )
                        begin
                                Cur_Color_R     <=      iCursor_R;
                                Cur_Color_G     <=      iCursor_G;
                                Cur_Color_B     <=      iCursor_B;
                        end
                        else
                        begin
                                Cur_Color_R     <=      iRed;
                                Cur_Color_G     <=      iGreen;
                                Cur_Color_B     <=      iBlue;
                        end
                end
                else
                begin
                        Cur_Color_R     <=      iRed;
                        Cur_Color_G     <=      iGreen;
                        Cur_Color_B     <=      iBlue;
                end
        end
end
 
//      H_Sync Generator, Ref. 25.175 MHz Clock
always@(posedge iCLK or negedge iRST_N)
begin
        if(!iRST_N)
        begin
                H_Cont          <=      0;
                oVGA_H_SYNC     <=      0;
        end
        else
        begin
                //      H_Sync Counter
                if( H_Cont < H_SYNC_TOTAL )
                H_Cont  <=      H_Cont+1;
                else
                H_Cont  <=      0;
                //      H_Sync Generator
                if( H_Cont < H_SYNC_CYC )
                oVGA_H_SYNC     <=      0;
                else
                oVGA_H_SYNC     <=      1;
        end
end
 
//      V_Sync Generator, Ref. H_Sync
always@(posedge iCLK or negedge iRST_N)
begin
        if(!iRST_N)
        begin
                V_Cont          <=      0;
                oVGA_V_SYNC     <=      0;
        end
        else
        begin
                //      When H_Sync Re-start
                if(H_Cont==0)
                begin
                        //      V_Sync Counter
                        if( V_Cont < V_SYNC_TOTAL )
                        V_Cont  <=      V_Cont+1;
                        else
                        V_Cont  <=      0;
                        //      V_Sync Generator
                        if(     V_Cont < V_SYNC_CYC )
                        oVGA_V_SYNC     <=      0;
                        else
                        oVGA_V_SYNC     <=      1;
                end
        end
end
 
endmodule

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Subversion Repositories z80control

[/] [z80control/] [trunk/] [CII_Starter_USB_API_v1/] [HW/] [VGA_Controller/] [VGA_Controller.v] - Blame information for rev 12

Line No.	Rev	Author	Line
1	12	tylerapohl	`//Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your`
2			`//use of Altera Corporation's design tools, logic functions and other`
3			`//software and tools, and its AMPP partner logic functions, and any`
4			`//output files any of the foregoing (including device programming or`
5			`//simulation files), and any associated documentation or information are`
6			`//expressly subject to the terms and conditions of the Altera Program`
7			`//License Subscription Agreement or other applicable license agreement,`
8			`//including, without limitation, that your use is for the sole purpose`
9			`//of programming logic devices manufactured by Altera and sold by Altera`
10			`//or its authorized distributors. Please refer to the applicable`
11			`//agreement for further details.`
12
13			`module VGA_Controller( // Host Side`
14			`iCursor_RGB_EN,`
15			`iCursor_X,`
16			`iCursor_Y,`
17			`iCursor_R,`
18			`iCursor_G,`
19			`iCursor_B,`
20			`iRed,`
21			`iGreen,`
22			`iBlue,`
23			`oAddress,`
24			`oCoord_X,`
25			`oCoord_Y,`
26			`// VGA Side`
27			`oVGA_R,`
28			`oVGA_G,`
29			`oVGA_B,`
30			`oVGA_H_SYNC,`
31			`oVGA_V_SYNC,`
32			`oVGA_SYNC,`
33			`oVGA_BLANK,`
34			`oVGA_CLOCK,`
35			`// Control Signal`
36			`iCLK,`
37			`iRST_N );`
38
39			`include "VGA_Param.h"
40
41			`// Host Side`
42			`output reg [19:0] oAddress;`
43			`output reg [9:0] oCoord_X;`
44			`output reg [9:0] oCoord_Y;`
45			`input [3:0] iCursor_RGB_EN;`
46			`input [9:0] iCursor_X;`
47			`input [9:0] iCursor_Y;`
48			`input [9:0] iCursor_R;`
49			`input [9:0] iCursor_G;`
50			`input [9:0] iCursor_B;`
51			`input [9:0] iRed;`
52			`input [9:0] iGreen;`
53			`input [9:0] iBlue;`
54			`// VGA Side`
55			`output [9:0] oVGA_R;`
56			`output [9:0] oVGA_G;`
57			`output [9:0] oVGA_B;`
58			`output reg oVGA_H_SYNC;`
59			`output reg oVGA_V_SYNC;`
60			`output oVGA_SYNC;`
61			`output oVGA_BLANK;`
62			`output oVGA_CLOCK;`
63			`// Control Signal`
64			`input iCLK;`
65			`input iRST_N;`
66
67			`// Internal Registers and Wires`
68			`reg [9:0] H_Cont;`
69			`reg [9:0] V_Cont;`
70			`reg [9:0] Cur_Color_R;`
71			`reg [9:0] Cur_Color_G;`
72			`reg [9:0] Cur_Color_B;`
73			`wire mCursor_EN;`
74			`wire mRed_EN;`
75			`wire mGreen_EN;`
76			`wire mBlue_EN;`
77
78			`assign oVGA_BLANK = oVGA_H_SYNC & oVGA_V_SYNC;`
79			`assign oVGA_SYNC = 1'b0;`
80			`assign oVGA_CLOCK = iCLK;`
81			`assign mCursor_EN = iCursor_RGB_EN[3];`
82			`assign mRed_EN = iCursor_RGB_EN[2];`
83			`assign mGreen_EN = iCursor_RGB_EN[1];`
84			`assign mBlue_EN = iCursor_RGB_EN[0];`
85
86			`assign oVGA_R = ( H_Cont>=X_START+9 && H_Cont<X_START+H_SYNC_ACT+9 &&`
87			`V_Cont>=Y_START && V_Cont<Y_START+V_SYNC_ACT )`
88			`? (mRed_EN ? Cur_Color_R : 0) : 0;`
89			`assign oVGA_G = ( H_Cont>=X_START+9 && H_Cont<X_START+H_SYNC_ACT+9 &&`
90			`V_Cont>=Y_START && V_Cont<Y_START+V_SYNC_ACT )`
91			`? (mGreen_EN ? Cur_Color_G : 0) : 0;`
92			`assign oVGA_B = ( H_Cont>=X_START+9 && H_Cont<X_START+H_SYNC_ACT+9 &&`
93			`V_Cont>=Y_START && V_Cont<Y_START+V_SYNC_ACT )`
94			`? (mBlue_EN ? Cur_Color_B : 0) : 0;`
95
96			`// Pixel LUT Address Generator`
97			`always@(posedge iCLK or negedge iRST_N)`
98			`begin`
99			`if(!iRST_N)`
100			`begin`
101			`oCoord_X <= 0;`
102			`oCoord_Y <= 0;`
103			`oAddress <= 0;`
104			`end`
105			`else`
106			`begin`
107			`if( H_Cont>=X_START && H_Cont<X_START+H_SYNC_ACT &&`
108			`V_Cont>=Y_START && V_Cont<Y_START+V_SYNC_ACT )`
109			`begin`
110			`oCoord_X <= H_Cont-X_START;`
111			`oCoord_Y <= V_Cont-Y_START;`
112			`oAddress <= oCoord_Y*H_SYNC_ACT+oCoord_X-3;`
113			`end`
114			`end`
115			`end`
116
117			`// Cursor Generator`
118			`always@(posedge iCLK or negedge iRST_N)`
119			`begin`
120			`if(!iRST_N)`
121			`begin`
122			`Cur_Color_R <= 0;`
123			`Cur_Color_G <= 0;`
124			`Cur_Color_B <= 0;`
125			`end`
126			`else`
127			`begin`
128			`if( H_Cont>=X_START+8 && H_Cont<X_START+H_SYNC_ACT+8 &&`
129			`V_Cont>=Y_START && V_Cont<Y_START+V_SYNC_ACT )`
130			`begin`
131			`if( ( (H_Cont==X_START + 8 + iCursor_X) \|\|`
132			`(H_Cont==X_START + 8 + iCursor_X+1) \|\|`
133			`(H_Cont==X_START + 8 + iCursor_X-1) \|\|`
134			`(V_Cont==Y_START + iCursor_Y) \|\|`
135			`(V_Cont==Y_START + iCursor_Y+1) \|\|`
136			`(V_Cont==Y_START + iCursor_Y-1) )`
137			`&& mCursor_EN )`
138			`begin`
139			`Cur_Color_R <= iCursor_R;`
140			`Cur_Color_G <= iCursor_G;`
141			`Cur_Color_B <= iCursor_B;`
142			`end`
143			`else`
144			`begin`
145			`Cur_Color_R <= iRed;`
146			`Cur_Color_G <= iGreen;`
147			`Cur_Color_B <= iBlue;`
148			`end`
149			`end`
150			`else`
151			`begin`
152			`Cur_Color_R <= iRed;`
153			`Cur_Color_G <= iGreen;`
154			`Cur_Color_B <= iBlue;`
155			`end`
156			`end`
157			`end`
158
159			`// H_Sync Generator, Ref. 25.175 MHz Clock`
160			`always@(posedge iCLK or negedge iRST_N)`
161			`begin`
162			`if(!iRST_N)`
163			`begin`
164			`H_Cont <= 0;`
165			`oVGA_H_SYNC <= 0;`
166			`end`
167			`else`
168			`begin`
169			`// H_Sync Counter`
170			`if( H_Cont < H_SYNC_TOTAL )`
171			`H_Cont <= H_Cont+1;`
172			`else`
173			`H_Cont <= 0;`
174			`// H_Sync Generator`
175			`if( H_Cont < H_SYNC_CYC )`
176			`oVGA_H_SYNC <= 0;`
177			`else`
178			`oVGA_H_SYNC <= 1;`
179			`end`
180			`end`
181
182			`// V_Sync Generator, Ref. H_Sync`
183			`always@(posedge iCLK or negedge iRST_N)`
184			`begin`
185			`if(!iRST_N)`
186			`begin`
187			`V_Cont <= 0;`
188			`oVGA_V_SYNC <= 0;`
189			`end`
190			`else`
191			`begin`
192			`// When H_Sync Re-start`
193			`if(H_Cont==0)`
194			`begin`
195			`// V_Sync Counter`
196			`if( V_Cont < V_SYNC_TOTAL )`
197			`V_Cont <= V_Cont+1;`
198			`else`
199			`V_Cont <= 0;`
200			`// V_Sync Generator`
201			`if( V_Cont < V_SYNC_CYC )`
202			`oVGA_V_SYNC <= 0;`
203			`else`
204			`oVGA_V_SYNC <= 1;`
205			`end`
206			`end`
207			`end`
208
209			`endmodule`