1 |
12 |
tylerapohl |
-- megafunction wizard: %LPM_AND%
|
2 |
|
|
-- GENERATION: STANDARD
|
3 |
|
|
-- VERSION: WM1.0
|
4 |
|
|
-- MODULE: lpm_and
|
5 |
|
|
|
6 |
|
|
-- ============================================================
|
7 |
|
|
-- File Name: lpm_and0.vhd
|
8 |
|
|
-- Megafunction Name(s):
|
9 |
|
|
-- lpm_and
|
10 |
|
|
--
|
11 |
|
|
-- Simulation Library Files(s):
|
12 |
|
|
-- lpm
|
13 |
|
|
-- ============================================================
|
14 |
|
|
-- ************************************************************
|
15 |
|
|
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
16 |
|
|
--
|
17 |
|
|
-- 8.1 Build 163 10/28/2008 SJ Web Edition
|
18 |
|
|
-- ************************************************************
|
19 |
|
|
|
20 |
|
|
|
21 |
|
|
--Copyright (C) 1991-2008 Altera Corporation
|
22 |
|
|
--Your use of Altera Corporation's design tools, logic functions
|
23 |
|
|
--and other software and tools, and its AMPP partner logic
|
24 |
|
|
--functions, and any output files from any of the foregoing
|
25 |
|
|
--(including device programming or simulation files), and any
|
26 |
|
|
--associated documentation or information are expressly subject
|
27 |
|
|
--to the terms and conditions of the Altera Program License
|
28 |
|
|
--Subscription Agreement, Altera MegaCore Function License
|
29 |
|
|
--Agreement, or other applicable license agreement, including,
|
30 |
|
|
--without limitation, that your use is for the sole purpose of
|
31 |
|
|
--programming logic devices manufactured by Altera and sold by
|
32 |
|
|
--Altera or its authorized distributors. Please refer to the
|
33 |
|
|
--applicable agreement for further details.
|
34 |
|
|
|
35 |
|
|
|
36 |
|
|
LIBRARY ieee;
|
37 |
|
|
USE ieee.std_logic_1164.all;
|
38 |
|
|
|
39 |
|
|
LIBRARY lpm;
|
40 |
|
|
USE lpm.lpm_components.all;
|
41 |
|
|
|
42 |
|
|
ENTITY lpm_and0 IS
|
43 |
|
|
PORT
|
44 |
|
|
(
|
45 |
|
|
data0 : IN STD_LOGIC ;
|
46 |
|
|
data1 : IN STD_LOGIC ;
|
47 |
|
|
result : OUT STD_LOGIC
|
48 |
|
|
);
|
49 |
|
|
END lpm_and0;
|
50 |
|
|
|
51 |
|
|
|
52 |
|
|
ARCHITECTURE SYN OF lpm_and0 IS
|
53 |
|
|
|
54 |
|
|
-- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
|
55 |
|
|
|
56 |
|
|
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0);
|
57 |
|
|
SIGNAL sub_wire1 : STD_LOGIC ;
|
58 |
|
|
SIGNAL sub_wire2 : STD_LOGIC ;
|
59 |
|
|
SIGNAL sub_wire3 : STD_LOGIC_2D (1 DOWNTO 0, 0 DOWNTO 0);
|
60 |
|
|
SIGNAL sub_wire4 : STD_LOGIC ;
|
61 |
|
|
|
62 |
|
|
BEGIN
|
63 |
|
|
sub_wire4 <= data0;
|
64 |
|
|
sub_wire1 <= sub_wire0(0);
|
65 |
|
|
result <= sub_wire1;
|
66 |
|
|
sub_wire2 <= data1;
|
67 |
|
|
sub_wire3(1, 0) <= sub_wire2;
|
68 |
|
|
sub_wire3(0, 0) <= sub_wire4;
|
69 |
|
|
|
70 |
|
|
lpm_and_component : lpm_and
|
71 |
|
|
GENERIC MAP (
|
72 |
|
|
lpm_size => 2,
|
73 |
|
|
lpm_type => "LPM_AND",
|
74 |
|
|
lpm_width => 1
|
75 |
|
|
)
|
76 |
|
|
PORT MAP (
|
77 |
|
|
data => sub_wire3,
|
78 |
|
|
result => sub_wire0
|
79 |
|
|
);
|
80 |
|
|
|
81 |
|
|
|
82 |
|
|
|
83 |
|
|
END SYN;
|
84 |
|
|
|
85 |
|
|
-- ============================================================
|
86 |
|
|
-- CNX file retrieval info
|
87 |
|
|
-- ============================================================
|
88 |
|
|
-- Retrieval info: PRIVATE: CompactSymbol NUMERIC "0"
|
89 |
|
|
-- Retrieval info: PRIVATE: GateFunction NUMERIC "0"
|
90 |
|
|
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
|
91 |
|
|
-- Retrieval info: PRIVATE: InputAsBus NUMERIC "0"
|
92 |
|
|
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
93 |
|
|
-- Retrieval info: PRIVATE: WidthInput NUMERIC "1"
|
94 |
|
|
-- Retrieval info: PRIVATE: nInput NUMERIC "2"
|
95 |
|
|
-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "2"
|
96 |
|
|
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_AND"
|
97 |
|
|
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
|
98 |
|
|
-- Retrieval info: USED_PORT: data0 0 0 0 0 INPUT NODEFVAL data0
|
99 |
|
|
-- Retrieval info: USED_PORT: data1 0 0 0 0 INPUT NODEFVAL data1
|
100 |
|
|
-- Retrieval info: USED_PORT: result 0 0 0 0 OUTPUT NODEFVAL result
|
101 |
|
|
-- Retrieval info: CONNECT: @data 1 0 1 0 data0 0 0 0 0
|
102 |
|
|
-- Retrieval info: CONNECT: @data 1 1 1 0 data1 0 0 0 0
|
103 |
|
|
-- Retrieval info: CONNECT: result 0 0 0 0 @result 0 0 1 0
|
104 |
|
|
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
105 |
|
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_and0.vhd TRUE
|
106 |
|
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_and0.inc FALSE
|
107 |
|
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_and0.cmp FALSE
|
108 |
|
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_and0.bsf TRUE FALSE
|
109 |
|
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_and0_inst.vhd FALSE
|
110 |
|
|
-- Retrieval info: LIB_FILE: lpm
|