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[/] [z80control/] [trunk/] [CII_Starter_USB_API_v1/] [HW/] [ps2_keyboard.v] - Blame information for rev 12

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//Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors.  Please refer to the applicable
//agreement for further details.
 
 
 
`define TOTAL_BITS   11
`define EXTEND_CODE  16'hE0
`define RELEASE_CODE 16'hF0
`define LEFT_SHIFT   16'h12
`define RIGHT_SHIFT  16'h59
 
 
module ps2_keyboard (
  clk,
  reset,
  ps2_clk_en_o_,
  ps2_data_en_o_,
  ps2_clk_i,
  ps2_data_i,
  rx_extended,
  rx_released,
  rx_shift_key_on,
  rx_scan_code,
  rx_ascii,
  rx_data_ready,       // rx_read_o
  rx_read,             // rx_read_ack_i
  tx_data,
  tx_write,
  tx_write_ack_o,
  tx_error_no_keyboard_ack,
  translate
  );
 
// Parameters
 
// The timer value can be up to (2^bits) inclusive.
parameter TIMER_60USEC_VALUE_PP = 2950; // Number of sys_clks for 60usec.
parameter TIMER_60USEC_BITS_PP  = 12;   // Number of bits needed for timer
parameter TIMER_5USEC_VALUE_PP = 186;   // Number of sys_clks for debounce
parameter TIMER_5USEC_BITS_PP  = 8;     // Number of bits needed for timer
parameter TRAP_SHIFT_KEYS_PP = 0;       // Default: No shift key trap.
 
// State encodings, provided as parameters
// for flexibility to the one instantiating the module.
// In general, the default values need not be changed.
 
// State "m1_rx_clk_l" has been chosen on purpose.  Since the input
// synchronizing flip-flops initially contain zero, it takes one clk
// for them to update to reflect the actual (idle = high) status of
// the I/O lines from the keyboard.  Therefore, choosing 0 for m1_rx_clk_l
// allows the state machine to transition to m1_rx_clk_h when the true
// values of the input signals become present at the outputs of the
// synchronizing flip-flops.  This initial transition is harmless, and it
// eliminates the need for a "reset" pulse before the interface can operate.
 
parameter m1_rx_clk_h = 1;
parameter m1_rx_clk_l = 0;
parameter m1_rx_falling_edge_marker = 13;
parameter m1_rx_rising_edge_marker = 14;
parameter m1_tx_force_clk_l = 3;
parameter m1_tx_first_wait_clk_h = 10;
parameter m1_tx_first_wait_clk_l = 11;
parameter m1_tx_reset_timer = 12;
parameter m1_tx_wait_clk_h = 2;
parameter m1_tx_clk_h = 4;
parameter m1_tx_clk_l = 5;
parameter m1_tx_wait_keyboard_ack = 6;
parameter m1_tx_done_recovery = 7;
parameter m1_tx_error_no_keyboard_ack = 8;
parameter m1_tx_rising_edge_marker = 9;
parameter m2_rx_data_ready = 1;
parameter m2_rx_data_ready_ack = 0;
 
 
// I/O declarations
input clk;
input reset;
output ps2_clk_en_o_ ;
output ps2_data_en_o_ ;
input  ps2_clk_i ;
input  ps2_data_i ;
output rx_extended;
output rx_released;
output rx_shift_key_on;
output [7:0] rx_scan_code;
output [7:0] rx_ascii;
output rx_data_ready;
input rx_read;
input [7:0] tx_data;
input tx_write;
output tx_write_ack_o;
output tx_error_no_keyboard_ack;
input  translate ;
 
reg rx_extended;
reg rx_released;
reg [7:0] rx_scan_code;
reg [7:0] rx_ascii;
reg rx_data_ready;
reg tx_error_no_keyboard_ack;
 
// Internal signal declarations
wire timer_60usec_done;
wire timer_5usec_done;
wire extended;
wire released;
wire shift_key_on;
 
                         // NOTE: These two signals used to be one.  They
                         //       were split into two signals because of
                         //       shift key trapping.  With shift key
                         //       trapping, no event is generated externally,
                         //       but the "hold" data must still be cleared
                         //       anyway regardless, in preparation for the
                         //       next scan codes.
wire rx_output_event;    // Used only to clear: hold_released, hold_extended
wire rx_output_strobe;   // Used to produce the actual output.
 
wire tx_parity_bit;
wire rx_shifting_done;
wire tx_shifting_done;
wire [11:0] shift_key_plus_code;
 
reg [`TOTAL_BITS-1:0] q;
reg [3:0] m1_state;
reg [3:0] m1_next_state;
reg m2_state;
reg m2_next_state;
reg [3:0] bit_count;
reg enable_timer_60usec;
reg enable_timer_5usec;
reg [TIMER_60USEC_BITS_PP-1:0] timer_60usec_count;
reg [TIMER_5USEC_BITS_PP-1:0] timer_5usec_count;
reg [7:0] ascii;      // "REG" type only because a case statement is used.
reg left_shift_key;
reg right_shift_key;
reg hold_extended;    // Holds prior value, cleared at rx_output_strobe
reg hold_released;    // Holds prior value, cleared at rx_output_strobe
reg ps2_clk_s;        // Synchronous version of this input
reg ps2_data_s;       // Synchronous version of this input
reg ps2_clk_hi_z;     // Without keyboard, high Z equals 1 due to pullups.
reg ps2_data_hi_z;    // Without keyboard, high Z equals 1 due to pullups.
 
//--------------------------------------------------------------------------
// Module code
 
assign ps2_clk_en_o_  = ps2_clk_hi_z  ;
assign ps2_data_en_o_ = ps2_data_hi_z ;
 
// Input "synchronizing" logic -- synchronizes the inputs to the state
// machine clock, thus avoiding errors related to
// spurious state machine transitions.
always @(posedge clk)
begin
  ps2_clk_s <= ps2_clk_i;
  ps2_data_s <= ps2_data_i;
end
 
// State register
always @(posedge clk)
begin : m1_state_register
  if (reset) m1_state <= m1_rx_clk_h;
  else m1_state <= m1_next_state;
end
 
// State transition logic
always @(m1_state
         or q
         or tx_shifting_done
         or tx_write
         or ps2_clk_s
         or ps2_data_s
         or timer_60usec_done
         or timer_5usec_done
         )
begin : m1_state_logic
 
  // Output signals default to this value, unless changed in a state condition.
  ps2_clk_hi_z <= 1;
  ps2_data_hi_z <= 1;
  tx_error_no_keyboard_ack <= 0;
  enable_timer_60usec <= 0;
  enable_timer_5usec <= 0;
 
  case (m1_state)
 
    m1_rx_clk_h :
      begin
        enable_timer_60usec <= 1;
        if (tx_write) m1_next_state <= m1_tx_reset_timer;
        else if (~ps2_clk_s) m1_next_state <= m1_rx_falling_edge_marker;
        else m1_next_state <= m1_rx_clk_h;
      end
 
    m1_rx_falling_edge_marker :
      begin
        enable_timer_60usec <= 0;
        m1_next_state <= m1_rx_clk_l;
      end
 
    m1_rx_rising_edge_marker :
      begin
        enable_timer_60usec <= 0;
        m1_next_state <= m1_rx_clk_h;
      end
 
 
    m1_rx_clk_l :
      begin
        enable_timer_60usec <= 1;
        if (tx_write) m1_next_state <= m1_tx_reset_timer;
        else if (ps2_clk_s) m1_next_state <= m1_rx_rising_edge_marker;
        else m1_next_state <= m1_rx_clk_l;
      end
 
    m1_tx_reset_timer:
      begin
        enable_timer_60usec <= 0;
        m1_next_state <= m1_tx_force_clk_l;
      end
 
    m1_tx_force_clk_l :
      begin
        enable_timer_60usec <= 1;
        ps2_clk_hi_z <= 0;  // Force the ps2_clk line low.
        if (timer_60usec_done) m1_next_state <= m1_tx_first_wait_clk_h;
        else m1_next_state <= m1_tx_force_clk_l;
      end
 
    m1_tx_first_wait_clk_h :
      begin
        enable_timer_5usec <= 1;
        ps2_data_hi_z <= 0;        // Start bit.
        if (~ps2_clk_s && timer_5usec_done)
          m1_next_state <= m1_tx_clk_l;
        else
          m1_next_state <= m1_tx_first_wait_clk_h;
      end
 
    // This state must be included because the device might possibly
    // delay for up to 10 milliseconds before beginning its clock pulses.
    // During that waiting time, we cannot drive the data (q[0]) because it
    // is possibly 1, which would cause the keyboard to abort its receive
    // and the expected clocks would then never be generated.
    m1_tx_first_wait_clk_l :
      begin
        ps2_data_hi_z <= 0;
        if (~ps2_clk_s) m1_next_state <= m1_tx_clk_l;
        else m1_next_state <= m1_tx_first_wait_clk_l;
      end
 
    m1_tx_wait_clk_h :
      begin
        enable_timer_5usec <= 1;
        ps2_data_hi_z <= q[0];
        if (ps2_clk_s && timer_5usec_done)
          m1_next_state <= m1_tx_rising_edge_marker;
        else
          m1_next_state <= m1_tx_wait_clk_h;
      end
 
    m1_tx_rising_edge_marker :
      begin
        ps2_data_hi_z <= q[0];
        m1_next_state <= m1_tx_clk_h;
      end
 
    m1_tx_clk_h :
      begin
        ps2_data_hi_z <= q[0];
        if (tx_shifting_done) m1_next_state <= m1_tx_wait_keyboard_ack;
        else if (~ps2_clk_s) m1_next_state <= m1_tx_clk_l;
        else m1_next_state <= m1_tx_clk_h;
      end
 
    m1_tx_clk_l :
      begin
        ps2_data_hi_z <= q[0];
        if (ps2_clk_s) m1_next_state <= m1_tx_wait_clk_h;
        else m1_next_state <= m1_tx_clk_l;
      end
 
    m1_tx_wait_keyboard_ack :
      begin
        if (~ps2_clk_s && ps2_data_s)
          m1_next_state <= m1_tx_error_no_keyboard_ack;
        else if (~ps2_clk_s && ~ps2_data_s)
          m1_next_state <= m1_tx_done_recovery;
        else m1_next_state <= m1_tx_wait_keyboard_ack;
      end
 
    m1_tx_done_recovery :
      begin
        if (ps2_clk_s && ps2_data_s) m1_next_state <= m1_rx_clk_h;
        else m1_next_state <= m1_tx_done_recovery;
      end
 
    m1_tx_error_no_keyboard_ack :
      begin
        tx_error_no_keyboard_ack <= 1;
        if (ps2_clk_s && ps2_data_s) m1_next_state <= m1_rx_clk_h;
        else m1_next_state <= m1_tx_error_no_keyboard_ack;
      end
 
    default : m1_next_state <= m1_rx_clk_h;
  endcase
end
 
// State register
always @(posedge clk)
begin : m2_state_register
  if (reset) m2_state <= m2_rx_data_ready_ack;
  else m2_state <= m2_next_state;
end
 
// State transition logic
always @(m2_state or rx_output_strobe or rx_read)
begin : m2_state_logic
  case (m2_state)
    m2_rx_data_ready_ack:
          begin
            rx_data_ready <= 1'b0;
            if (rx_output_strobe) m2_next_state <= m2_rx_data_ready;
            else m2_next_state <= m2_rx_data_ready_ack;
          end
    m2_rx_data_ready:
          begin
            rx_data_ready <= 1'b1;
            if (rx_read) m2_next_state <= m2_rx_data_ready_ack;
            else m2_next_state <= m2_rx_data_ready;
          end
    default : m2_next_state <= m2_rx_data_ready_ack;
  endcase
end
 
// This is the bit counter
always @(posedge clk)
begin
  if (   reset
      || rx_shifting_done
      || (m1_state == m1_tx_wait_keyboard_ack)        // After tx is done.
      ) bit_count <= 0;  // normal reset
  else if (timer_60usec_done
           && (m1_state == m1_rx_clk_h)
           && (ps2_clk_s)
      ) bit_count <= 0;  // rx watchdog timer reset
  else if ( (m1_state == m1_rx_falling_edge_marker)   // increment for rx
           ||(m1_state == m1_tx_rising_edge_marker)   // increment for tx
           )
    bit_count <= bit_count + 1;
end
// This signal is high for one clock at the end of the timer count.
assign rx_shifting_done = (bit_count == `TOTAL_BITS);
assign tx_shifting_done = (bit_count == `TOTAL_BITS-1);
 
// This is the signal which enables loading of the shift register.
// It also indicates "ack" to the device writing to the transmitter.
assign tx_write_ack_o = (  (tx_write && (m1_state == m1_rx_clk_h))
                         ||(tx_write && (m1_state == m1_rx_clk_l))
                         );
 
// This is the ODD parity bit for the transmitted word.
assign tx_parity_bit = ~^tx_data;
 
// This is the shift register
always @(posedge clk)
begin
  if (reset) q <= 0;
  else if (tx_write_ack_o) q <= {1'b1,tx_parity_bit,tx_data,1'b0};
  else if ( (m1_state == m1_rx_falling_edge_marker)
           ||(m1_state == m1_tx_rising_edge_marker) )
    q <= {ps2_data_s,q[`TOTAL_BITS-1:1]};
end
 
// This is the 60usec timer counter
always @(posedge clk)
begin
  if (~enable_timer_60usec) timer_60usec_count <= 0;
  else if (~timer_60usec_done) timer_60usec_count <= timer_60usec_count + 1;
end
assign timer_60usec_done = (timer_60usec_count == (TIMER_60USEC_VALUE_PP - 1));
 
// This is the 5usec timer counter
always @(posedge clk)
begin
  if (~enable_timer_5usec) timer_5usec_count <= 0;
  else if (~timer_5usec_done) timer_5usec_count <= timer_5usec_count + 1;
end
assign timer_5usec_done = (timer_5usec_count == TIMER_5USEC_VALUE_PP - 1);
 
 
// Create the signals which indicate special scan codes received.
// These are the "unlatched versions."
`ifdef PS2_TRAP_EXTENDED
assign extended = (q[8:1] == `EXTEND_CODE) && rx_shifting_done && translate ;
`else
assign extended = 1'b0 ;
`endif
assign released = (q[8:1] == `RELEASE_CODE) && rx_shifting_done && translate ;
 
// Store the special scan code status bits
// Not the final output, but an intermediate storage place,
// until the entire set of output data can be assembled.
always @(posedge clk)
begin
  if (reset || rx_output_event)
  begin
    hold_extended <= 0;
    hold_released <= 0;
  end
  else
  begin
    if (rx_shifting_done && extended) hold_extended <= 1;
    if (rx_shifting_done && released) hold_released <= 1;
  end
end
 
 
// These bits contain the status of the two shift keys
always @(posedge clk)
begin
  if (reset) left_shift_key <= 0;
  else if ((q[8:1] == `LEFT_SHIFT) && rx_shifting_done && ~hold_released)
    left_shift_key <= 1;
  else if ((q[8:1] == `LEFT_SHIFT) && rx_shifting_done && hold_released)
    left_shift_key <= 0;
end
 
always @(posedge clk)
begin
  if (reset) right_shift_key <= 0;
  else if ((q[8:1] == `RIGHT_SHIFT) && rx_shifting_done && ~hold_released)
    right_shift_key <= 1;
  else if ((q[8:1] == `RIGHT_SHIFT) && rx_shifting_done && hold_released)
    right_shift_key <= 0;
end
 
assign rx_shift_key_on = left_shift_key || right_shift_key;
 
// Output the special scan code flags, the scan code and the ascii
always @(posedge clk)
begin
  if (reset)
  begin
    rx_extended <= 0;
    rx_released <= 0;
    rx_scan_code <= 0;
    rx_ascii <= 0;
  end
  else if (rx_output_strobe)
  begin
    rx_extended <= hold_extended;
    rx_released <= hold_released;
    rx_scan_code <= q[8:1];
    rx_ascii <= ascii;
  end
end
 
// Store the final rx output data only when all extend and release codes
// are received and the next (actual key) scan code is also ready.
// (the presence of rx_extended or rx_released refers to the
// the current latest scan code received, not the previously latched flags.)
assign rx_output_event  = (rx_shifting_done
                          && ~extended
                          && ~released
                          );
 
assign rx_output_strobe = (rx_shifting_done
                          && ~extended
                          && ~released
                          && ( (TRAP_SHIFT_KEYS_PP == 0)
                               || ( (q[8:1] != `RIGHT_SHIFT)
                                    &&(q[8:1] != `LEFT_SHIFT)
                                  )
                             )
                          );
 
// This part translates the scan code into an ASCII value...
// Only the ASCII codes which I considered important have been included.
// if you want more, just add the appropriate case statement lines...
// (You will need to know the keyboard scan codes you wish to assign.)
// The entries are listed in ascending order of ASCII value.
assign shift_key_plus_code = {3'b0,rx_shift_key_on,q[8:1]};
always @(shift_key_plus_code)
begin
  casez (shift_key_plus_code)
    12'h?66 : ascii <= 8'h08;  // Backspace ("backspace" key)
    12'h?0d : ascii <= 8'h09;  // Horizontal Tab
    12'h?5a : ascii <= 8'h0d;  // Carriage return ("enter" key)
    12'h?76 : ascii <= 8'h1b;  // Escape ("esc" key)
    12'h?29 : ascii <= 8'h20;  // Space
    12'h116 : ascii <= 8'h21;  // !
    12'h152 : ascii <= 8'h22;  // "
    12'h126 : ascii <= 8'h23;  // #
    12'h125 : ascii <= 8'h24;  // $
    12'h12e : ascii <= 8'h25;  // %
    12'h13d : ascii <= 8'h26;  // &
    12'h052 : ascii <= 8'h27;  // '
    12'h146 : ascii <= 8'h28;  // (
    12'h145 : ascii <= 8'h29;  // )
    12'h13e : ascii <= 8'h2a;  // *
    12'h155 : ascii <= 8'h2b;  // +
    12'h041 : ascii <= 8'h2c;  // ,
    12'h04e : ascii <= 8'h2d;  // -
    12'h049 : ascii <= 8'h2e;  // .
    12'h04a : ascii <= 8'h2f;  // /
    12'h045 : ascii <= 8'h30;  // 0
    12'h016 : ascii <= 8'h31;  // 1
    12'h01e : ascii <= 8'h32;  // 2
    12'h026 : ascii <= 8'h33;  // 3
    12'h025 : ascii <= 8'h34;  // 4
    12'h02e : ascii <= 8'h35;  // 5
    12'h036 : ascii <= 8'h36;  // 6
    12'h03d : ascii <= 8'h37;  // 7
    12'h03e : ascii <= 8'h38;  // 8
    12'h046 : ascii <= 8'h39;  // 9
    12'h14c : ascii <= 8'h3a;  // :
    12'h04c : ascii <= 8'h3b;  // ;
    12'h141 : ascii <= 8'h3c;  // <
    12'h055 : ascii <= 8'h3d;  // =
    12'h149 : ascii <= 8'h3e;  // >
    12'h14a : ascii <= 8'h3f;  // ?
    12'h11e : ascii <= 8'h40;  // @
    12'h11c : ascii <= 8'h41;  // A
    12'h132 : ascii <= 8'h42;  // B
    12'h121 : ascii <= 8'h43;  // C
    12'h123 : ascii <= 8'h44;  // D
    12'h124 : ascii <= 8'h45;  // E
    12'h12b : ascii <= 8'h46;  // F
    12'h134 : ascii <= 8'h47;  // G
    12'h133 : ascii <= 8'h48;  // H
    12'h143 : ascii <= 8'h49;  // I
    12'h13b : ascii <= 8'h4a;  // J
    12'h142 : ascii <= 8'h4b;  // K
    12'h14b : ascii <= 8'h4c;  // L
    12'h13a : ascii <= 8'h4d;  // M
    12'h131 : ascii <= 8'h4e;  // N
    12'h144 : ascii <= 8'h4f;  // O
    12'h14d : ascii <= 8'h50;  // P
    12'h115 : ascii <= 8'h51;  // Q
    12'h12d : ascii <= 8'h52;  // R
    12'h11b : ascii <= 8'h53;  // S
    12'h12c : ascii <= 8'h54;  // T
    12'h13c : ascii <= 8'h55;  // U
    12'h12a : ascii <= 8'h56;  // V
    12'h11d : ascii <= 8'h57;  // W
    12'h122 : ascii <= 8'h58;  // X
    12'h135 : ascii <= 8'h59;  // Y
    12'h11a : ascii <= 8'h5a;  // Z
    12'h054 : ascii <= 8'h5b;  // [
    12'h05d : ascii <= 8'h5c;  // \
    12'h05b : ascii <= 8'h5d;  // ]
    12'h136 : ascii <= 8'h5e;  // ^
    12'h14e : ascii <= 8'h5f;  // _    
    12'h00e : ascii <= 8'h60;  // `
    12'h01c : ascii <= 8'h61;  // a
    12'h032 : ascii <= 8'h62;  // b
    12'h021 : ascii <= 8'h63;  // c
    12'h023 : ascii <= 8'h64;  // d
    12'h024 : ascii <= 8'h65;  // e
    12'h02b : ascii <= 8'h66;  // f
    12'h034 : ascii <= 8'h67;  // g
    12'h033 : ascii <= 8'h68;  // h
    12'h043 : ascii <= 8'h69;  // i
    12'h03b : ascii <= 8'h6a;  // j
    12'h042 : ascii <= 8'h6b;  // k
    12'h04b : ascii <= 8'h6c;  // l
    12'h03a : ascii <= 8'h6d;  // m
    12'h031 : ascii <= 8'h6e;  // n
    12'h044 : ascii <= 8'h6f;  // o
    12'h04d : ascii <= 8'h70;  // p
    12'h015 : ascii <= 8'h71;  // q
    12'h02d : ascii <= 8'h72;  // r
    12'h01b : ascii <= 8'h73;  // s
    12'h02c : ascii <= 8'h74;  // t
    12'h03c : ascii <= 8'h75;  // u
    12'h02a : ascii <= 8'h76;  // v
    12'h01d : ascii <= 8'h77;  // w
    12'h022 : ascii <= 8'h78;  // x
    12'h035 : ascii <= 8'h79;  // y
    12'h01a : ascii <= 8'h7a;  // z
    12'h154 : ascii <= 8'h7b;  // {
    12'h15d : ascii <= 8'h7c;  // |
    12'h15b : ascii <= 8'h7d;  // }
    12'h10e : ascii <= 8'h7e;  // ~
    12'h?71 : ascii <= 8'h7f;  // (Delete OR DEL on numeric keypad)
    default : ascii <= 8'h2e;  // '.' used for unlisted characters.
  endcase
end
 
 
endmodule
 
//`undefine TOTAL_BITS
//`undefine EXTEND_CODE
//`undefine RELEASE_CODE
//`undefine LEFT_SHIFT
//`undefine RIGHT_SHIFT
 

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[/] [z80control/] [trunk/] [CII_Starter_USB_API_v1/] [HW/] [ps2_keyboard.v] - Blame information for rev 12

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1	12	tylerapohl	`//Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your`
2			`//use of Altera Corporation's design tools, logic functions and other`
3			`//software and tools, and its AMPP partner logic functions, and any`
4			`//output files any of the foregoing (including device programming or`
5			`//simulation files), and any associated documentation or information are`
6			`//expressly subject to the terms and conditions of the Altera Program`
7			`//License Subscription Agreement or other applicable license agreement,`
8			`//including, without limitation, that your use is for the sole purpose`
9			`//of programming logic devices manufactured by Altera and sold by Altera`
10			`//or its authorized distributors. Please refer to the applicable`
11			`//agreement for further details.`
12
13
14
15			`define TOTAL_BITS 11
16			`define EXTEND_CODE 16'hE0
17			`define RELEASE_CODE 16'hF0
18			`define LEFT_SHIFT 16'h12
19			`define RIGHT_SHIFT 16'h59
20
21
22			`module ps2_keyboard (`
23			`clk,`
24			`reset,`
25			`ps2_clk_en_o_,`
26			`ps2_data_en_o_,`
27			`ps2_clk_i,`
28			`ps2_data_i,`
29			`rx_extended,`
30			`rx_released,`
31			`rx_shift_key_on,`
32			`rx_scan_code,`
33			`rx_ascii,`
34			`rx_data_ready, // rx_read_o`
35			`rx_read, // rx_read_ack_i`
36			`tx_data,`
37			`tx_write,`
38			`tx_write_ack_o,`
39			`tx_error_no_keyboard_ack,`
40			`translate`
41			`);`
42
43			`// Parameters`
44
45			`// The timer value can be up to (2^bits) inclusive.`
46			`parameter TIMER_60USEC_VALUE_PP = 2950; // Number of sys_clks for 60usec.`
47			`parameter TIMER_60USEC_BITS_PP = 12; // Number of bits needed for timer`
48			`parameter TIMER_5USEC_VALUE_PP = 186; // Number of sys_clks for debounce`
49			`parameter TIMER_5USEC_BITS_PP = 8; // Number of bits needed for timer`
50			`parameter TRAP_SHIFT_KEYS_PP = 0; // Default: No shift key trap.`
51
52			`// State encodings, provided as parameters`
53			`// for flexibility to the one instantiating the module.`
54			`// In general, the default values need not be changed.`
55
56			`// State "m1_rx_clk_l" has been chosen on purpose. Since the input`
57			`// synchronizing flip-flops initially contain zero, it takes one clk`
58			`// for them to update to reflect the actual (idle = high) status of`
59			`// the I/O lines from the keyboard. Therefore, choosing 0 for m1_rx_clk_l`
60			`// allows the state machine to transition to m1_rx_clk_h when the true`
61			`// values of the input signals become present at the outputs of the`
62			`// synchronizing flip-flops. This initial transition is harmless, and it`
63			`// eliminates the need for a "reset" pulse before the interface can operate.`
64
65			`parameter m1_rx_clk_h = 1;`
66			`parameter m1_rx_clk_l = 0;`
67			`parameter m1_rx_falling_edge_marker = 13;`
68			`parameter m1_rx_rising_edge_marker = 14;`
69			`parameter m1_tx_force_clk_l = 3;`
70			`parameter m1_tx_first_wait_clk_h = 10;`
71			`parameter m1_tx_first_wait_clk_l = 11;`
72			`parameter m1_tx_reset_timer = 12;`
73			`parameter m1_tx_wait_clk_h = 2;`
74			`parameter m1_tx_clk_h = 4;`
75			`parameter m1_tx_clk_l = 5;`
76			`parameter m1_tx_wait_keyboard_ack = 6;`
77			`parameter m1_tx_done_recovery = 7;`
78			`parameter m1_tx_error_no_keyboard_ack = 8;`
79			`parameter m1_tx_rising_edge_marker = 9;`
80			`parameter m2_rx_data_ready = 1;`
81			`parameter m2_rx_data_ready_ack = 0;`
82
83
84			`// I/O declarations`
85			`input clk;`
86			`input reset;`
87			`output ps2_clk_en_o_ ;`
88			`output ps2_data_en_o_ ;`
89			`input ps2_clk_i ;`
90			`input ps2_data_i ;`
91			`output rx_extended;`
92			`output rx_released;`
93			`output rx_shift_key_on;`
94			`output [7:0] rx_scan_code;`
95			`output [7:0] rx_ascii;`
96			`output rx_data_ready;`
97			`input rx_read;`
98			`input [7:0] tx_data;`
99			`input tx_write;`
100			`output tx_write_ack_o;`
101			`output tx_error_no_keyboard_ack;`
102			`input translate ;`
103
104			`reg rx_extended;`
105			`reg rx_released;`
106			`reg [7:0] rx_scan_code;`
107			`reg [7:0] rx_ascii;`
108			`reg rx_data_ready;`
109			`reg tx_error_no_keyboard_ack;`
110
111			`// Internal signal declarations`
112			`wire timer_60usec_done;`
113			`wire timer_5usec_done;`
114			`wire extended;`
115			`wire released;`
116			`wire shift_key_on;`
117
118			`// NOTE: These two signals used to be one. They`
119			`// were split into two signals because of`
120			`// shift key trapping. With shift key`
121			`// trapping, no event is generated externally,`
122			`// but the "hold" data must still be cleared`
123			`// anyway regardless, in preparation for the`
124			`// next scan codes.`
125			`wire rx_output_event; // Used only to clear: hold_released, hold_extended`
126			`wire rx_output_strobe; // Used to produce the actual output.`
127
128			`wire tx_parity_bit;`
129			`wire rx_shifting_done;`
130			`wire tx_shifting_done;`
131			`wire [11:0] shift_key_plus_code;`
132
133			reg [`TOTAL_BITS-1:0] q;
134			`reg [3:0] m1_state;`
135			`reg [3:0] m1_next_state;`
136			`reg m2_state;`
137			`reg m2_next_state;`
138			`reg [3:0] bit_count;`
139			`reg enable_timer_60usec;`
140			`reg enable_timer_5usec;`
141			`reg [TIMER_60USEC_BITS_PP-1:0] timer_60usec_count;`
142			`reg [TIMER_5USEC_BITS_PP-1:0] timer_5usec_count;`
143			`reg [7:0] ascii; // "REG" type only because a case statement is used.`
144			`reg left_shift_key;`
145			`reg right_shift_key;`
146			`reg hold_extended; // Holds prior value, cleared at rx_output_strobe`
147			`reg hold_released; // Holds prior value, cleared at rx_output_strobe`
148			`reg ps2_clk_s; // Synchronous version of this input`
149			`reg ps2_data_s; // Synchronous version of this input`
150			`reg ps2_clk_hi_z; // Without keyboard, high Z equals 1 due to pullups.`
151			`reg ps2_data_hi_z; // Without keyboard, high Z equals 1 due to pullups.`
152
153			`//--------------------------------------------------------------------------`
154			`// Module code`
155
156			`assign ps2_clk_en_o_ = ps2_clk_hi_z ;`
157			`assign ps2_data_en_o_ = ps2_data_hi_z ;`
158
159			`// Input "synchronizing" logic -- synchronizes the inputs to the state`
160			`// machine clock, thus avoiding errors related to`
161			`// spurious state machine transitions.`
162			`always @(posedge clk)`
163			`begin`
164			`ps2_clk_s <= ps2_clk_i;`
165			`ps2_data_s <= ps2_data_i;`
166			`end`
167
168			`// State register`
169			`always @(posedge clk)`
170			`begin : m1_state_register`
171			`if (reset) m1_state <= m1_rx_clk_h;`
172			`else m1_state <= m1_next_state;`
173			`end`
174
175			`// State transition logic`
176			`always @(m1_state`
177			`or q`
178			`or tx_shifting_done`
179			`or tx_write`
180			`or ps2_clk_s`
181			`or ps2_data_s`
182			`or timer_60usec_done`
183			`or timer_5usec_done`
184			`)`
185			`begin : m1_state_logic`
186
187			`// Output signals default to this value, unless changed in a state condition.`
188			`ps2_clk_hi_z <= 1;`
189			`ps2_data_hi_z <= 1;`
190			`tx_error_no_keyboard_ack <= 0;`
191			`enable_timer_60usec <= 0;`
192			`enable_timer_5usec <= 0;`
193
194			`case (m1_state)`
195
196			`m1_rx_clk_h :`
197			`begin`
198			`enable_timer_60usec <= 1;`
199			`if (tx_write) m1_next_state <= m1_tx_reset_timer;`
200			`else if (~ps2_clk_s) m1_next_state <= m1_rx_falling_edge_marker;`
201			`else m1_next_state <= m1_rx_clk_h;`
202			`end`
203
204			`m1_rx_falling_edge_marker :`
205			`begin`
206			`enable_timer_60usec <= 0;`
207			`m1_next_state <= m1_rx_clk_l;`
208			`end`
209
210			`m1_rx_rising_edge_marker :`
211			`begin`
212			`enable_timer_60usec <= 0;`
213			`m1_next_state <= m1_rx_clk_h;`
214			`end`
215
216
217			`m1_rx_clk_l :`
218			`begin`
219			`enable_timer_60usec <= 1;`
220			`if (tx_write) m1_next_state <= m1_tx_reset_timer;`
221			`else if (ps2_clk_s) m1_next_state <= m1_rx_rising_edge_marker;`
222			`else m1_next_state <= m1_rx_clk_l;`
223			`end`
224
225			`m1_tx_reset_timer:`
226			`begin`
227			`enable_timer_60usec <= 0;`
228			`m1_next_state <= m1_tx_force_clk_l;`
229			`end`
230
231			`m1_tx_force_clk_l :`
232			`begin`
233			`enable_timer_60usec <= 1;`
234			`ps2_clk_hi_z <= 0; // Force the ps2_clk line low.`
235			`if (timer_60usec_done) m1_next_state <= m1_tx_first_wait_clk_h;`
236			`else m1_next_state <= m1_tx_force_clk_l;`
237			`end`
238
239			`m1_tx_first_wait_clk_h :`
240			`begin`
241			`enable_timer_5usec <= 1;`
242			`ps2_data_hi_z <= 0; // Start bit.`
243			`if (~ps2_clk_s && timer_5usec_done)`
244			`m1_next_state <= m1_tx_clk_l;`
245			`else`
246			`m1_next_state <= m1_tx_first_wait_clk_h;`
247			`end`
248
249			`// This state must be included because the device might possibly`
250			`// delay for up to 10 milliseconds before beginning its clock pulses.`
251			`// During that waiting time, we cannot drive the data (q[0]) because it`
252			`// is possibly 1, which would cause the keyboard to abort its receive`
253			`// and the expected clocks would then never be generated.`
254			`m1_tx_first_wait_clk_l :`
255			`begin`
256			`ps2_data_hi_z <= 0;`
257			`if (~ps2_clk_s) m1_next_state <= m1_tx_clk_l;`
258			`else m1_next_state <= m1_tx_first_wait_clk_l;`
259			`end`
260
261			`m1_tx_wait_clk_h :`
262			`begin`
263			`enable_timer_5usec <= 1;`
264			`ps2_data_hi_z <= q[0];`
265			`if (ps2_clk_s && timer_5usec_done)`
266			`m1_next_state <= m1_tx_rising_edge_marker;`
267			`else`
268			`m1_next_state <= m1_tx_wait_clk_h;`
269			`end`
270
271			`m1_tx_rising_edge_marker :`
272			`begin`
273			`ps2_data_hi_z <= q[0];`
274			`m1_next_state <= m1_tx_clk_h;`
275			`end`
276
277			`m1_tx_clk_h :`
278			`begin`
279			`ps2_data_hi_z <= q[0];`
280			`if (tx_shifting_done) m1_next_state <= m1_tx_wait_keyboard_ack;`
281			`else if (~ps2_clk_s) m1_next_state <= m1_tx_clk_l;`
282			`else m1_next_state <= m1_tx_clk_h;`
283			`end`
284
285			`m1_tx_clk_l :`
286			`begin`
287			`ps2_data_hi_z <= q[0];`
288			`if (ps2_clk_s) m1_next_state <= m1_tx_wait_clk_h;`
289			`else m1_next_state <= m1_tx_clk_l;`
290			`end`
291
292			`m1_tx_wait_keyboard_ack :`
293			`begin`
294			`if (~ps2_clk_s && ps2_data_s)`
295			`m1_next_state <= m1_tx_error_no_keyboard_ack;`
296			`else if (~ps2_clk_s && ~ps2_data_s)`
297			`m1_next_state <= m1_tx_done_recovery;`
298			`else m1_next_state <= m1_tx_wait_keyboard_ack;`
299			`end`
300
301			`m1_tx_done_recovery :`
302			`begin`
303			`if (ps2_clk_s && ps2_data_s) m1_next_state <= m1_rx_clk_h;`
304			`else m1_next_state <= m1_tx_done_recovery;`
305			`end`
306
307			`m1_tx_error_no_keyboard_ack :`
308			`begin`
309			`tx_error_no_keyboard_ack <= 1;`
310			`if (ps2_clk_s && ps2_data_s) m1_next_state <= m1_rx_clk_h;`
311			`else m1_next_state <= m1_tx_error_no_keyboard_ack;`
312			`end`
313
314			`default : m1_next_state <= m1_rx_clk_h;`
315			`endcase`
316			`end`
317
318			`// State register`
319			`always @(posedge clk)`
320			`begin : m2_state_register`
321			`if (reset) m2_state <= m2_rx_data_ready_ack;`
322			`else m2_state <= m2_next_state;`
323			`end`
324
325			`// State transition logic`
326			`always @(m2_state or rx_output_strobe or rx_read)`
327			`begin : m2_state_logic`
328			`case (m2_state)`
329			`m2_rx_data_ready_ack:`
330			`begin`
331			`rx_data_ready <= 1'b0;`
332			`if (rx_output_strobe) m2_next_state <= m2_rx_data_ready;`
333			`else m2_next_state <= m2_rx_data_ready_ack;`
334			`end`
335			`m2_rx_data_ready:`
336			`begin`
337			`rx_data_ready <= 1'b1;`
338			`if (rx_read) m2_next_state <= m2_rx_data_ready_ack;`
339			`else m2_next_state <= m2_rx_data_ready;`
340			`end`
341			`default : m2_next_state <= m2_rx_data_ready_ack;`
342			`endcase`
343			`end`
344
345			`// This is the bit counter`
346			`always @(posedge clk)`
347			`begin`
348			`if ( reset`
349			`\|\| rx_shifting_done`
350			`\|\| (m1_state == m1_tx_wait_keyboard_ack) // After tx is done.`
351			`) bit_count <= 0; // normal reset`
352			`else if (timer_60usec_done`
353			`&& (m1_state == m1_rx_clk_h)`
354			`&& (ps2_clk_s)`
355			`) bit_count <= 0; // rx watchdog timer reset`
356			`else if ( (m1_state == m1_rx_falling_edge_marker) // increment for rx`
357			`\|\|(m1_state == m1_tx_rising_edge_marker) // increment for tx`
358			`)`
359			`bit_count <= bit_count + 1;`
360			`end`
361			`// This signal is high for one clock at the end of the timer count.`
362			assign rx_shifting_done = (bit_count == `TOTAL_BITS);
363			assign tx_shifting_done = (bit_count == `TOTAL_BITS-1);
364
365			`// This is the signal which enables loading of the shift register.`
366			`// It also indicates "ack" to the device writing to the transmitter.`
367			`assign tx_write_ack_o = ( (tx_write && (m1_state == m1_rx_clk_h))`
368			`\|\|(tx_write && (m1_state == m1_rx_clk_l))`
369			`);`
370
371			`// This is the ODD parity bit for the transmitted word.`
372			`assign tx_parity_bit = ~^tx_data;`
373
374			`// This is the shift register`
375			`always @(posedge clk)`
376			`begin`
377			`if (reset) q <= 0;`
378			`else if (tx_write_ack_o) q <= {1'b1,tx_parity_bit,tx_data,1'b0};`
379			`else if ( (m1_state == m1_rx_falling_edge_marker)`
380			`\|\|(m1_state == m1_tx_rising_edge_marker) )`
381			q <= {ps2_data_s,q[`TOTAL_BITS-1:1]};
382			`end`
383
384			`// This is the 60usec timer counter`
385			`always @(posedge clk)`
386			`begin`
387			`if (~enable_timer_60usec) timer_60usec_count <= 0;`
388			`else if (~timer_60usec_done) timer_60usec_count <= timer_60usec_count + 1;`
389			`end`
390			`assign timer_60usec_done = (timer_60usec_count == (TIMER_60USEC_VALUE_PP - 1));`
391
392			`// This is the 5usec timer counter`
393			`always @(posedge clk)`
394			`begin`
395			`if (~enable_timer_5usec) timer_5usec_count <= 0;`
396			`else if (~timer_5usec_done) timer_5usec_count <= timer_5usec_count + 1;`
397			`end`
398			`assign timer_5usec_done = (timer_5usec_count == TIMER_5USEC_VALUE_PP - 1);`
399
400
401			`// Create the signals which indicate special scan codes received.`
402			`// These are the "unlatched versions."`
403			`ifdef PS2_TRAP_EXTENDED
404			assign extended = (q[8:1] == `EXTEND_CODE) && rx_shifting_done && translate ;
405			`else
406			`assign extended = 1'b0 ;`
407			`endif
408			assign released = (q[8:1] == `RELEASE_CODE) && rx_shifting_done && translate ;
409
410			`// Store the special scan code status bits`
411			`// Not the final output, but an intermediate storage place,`
412			`// until the entire set of output data can be assembled.`
413			`always @(posedge clk)`
414			`begin`
415			`if (reset \|\| rx_output_event)`
416			`begin`
417			`hold_extended <= 0;`
418			`hold_released <= 0;`
419			`end`
420			`else`
421			`begin`
422			`if (rx_shifting_done && extended) hold_extended <= 1;`
423			`if (rx_shifting_done && released) hold_released <= 1;`
424			`end`
425			`end`
426
427
428			`// These bits contain the status of the two shift keys`
429			`always @(posedge clk)`
430			`begin`
431			`if (reset) left_shift_key <= 0;`
432			else if ((q[8:1] == `LEFT_SHIFT) && rx_shifting_done && ~hold_released)
433			`left_shift_key <= 1;`
434			else if ((q[8:1] == `LEFT_SHIFT) && rx_shifting_done && hold_released)
435			`left_shift_key <= 0;`
436			`end`
437
438			`always @(posedge clk)`
439			`begin`
440			`if (reset) right_shift_key <= 0;`
441			else if ((q[8:1] == `RIGHT_SHIFT) && rx_shifting_done && ~hold_released)
442			`right_shift_key <= 1;`
443			else if ((q[8:1] == `RIGHT_SHIFT) && rx_shifting_done && hold_released)
444			`right_shift_key <= 0;`
445			`end`
446
447			`assign rx_shift_key_on = left_shift_key \|\| right_shift_key;`
448
449			`// Output the special scan code flags, the scan code and the ascii`
450			`always @(posedge clk)`
451			`begin`
452			`if (reset)`
453			`begin`
454			`rx_extended <= 0;`
455			`rx_released <= 0;`
456			`rx_scan_code <= 0;`
457			`rx_ascii <= 0;`
458			`end`
459			`else if (rx_output_strobe)`
460			`begin`
461			`rx_extended <= hold_extended;`
462			`rx_released <= hold_released;`
463			`rx_scan_code <= q[8:1];`
464			`rx_ascii <= ascii;`
465			`end`
466			`end`
467
468			`// Store the final rx output data only when all extend and release codes`
469			`// are received and the next (actual key) scan code is also ready.`
470			`// (the presence of rx_extended or rx_released refers to the`
471			`// the current latest scan code received, not the previously latched flags.)`
472			`assign rx_output_event = (rx_shifting_done`
473			`&& ~extended`
474			`&& ~released`
475			`);`
476
477			`assign rx_output_strobe = (rx_shifting_done`
478			`&& ~extended`
479			`&& ~released`
480			`&& ( (TRAP_SHIFT_KEYS_PP == 0)`
481			\|\| ( (q[8:1] != `RIGHT_SHIFT)
482			&&(q[8:1] != `LEFT_SHIFT)
483			`)`
484			`)`
485			`);`
486
487			`// This part translates the scan code into an ASCII value...`
488			`// Only the ASCII codes which I considered important have been included.`
489			`// if you want more, just add the appropriate case statement lines...`
490			`// (You will need to know the keyboard scan codes you wish to assign.)`
491			`// The entries are listed in ascending order of ASCII value.`
492			`assign shift_key_plus_code = {3'b0,rx_shift_key_on,q[8:1]};`
493			`always @(shift_key_plus_code)`
494			`begin`
495			`casez (shift_key_plus_code)`
496			`12'h?66 : ascii <= 8'h08; // Backspace ("backspace" key)`
497			`12'h?0d : ascii <= 8'h09; // Horizontal Tab`
498			`12'h?5a : ascii <= 8'h0d; // Carriage return ("enter" key)`
499			`12'h?76 : ascii <= 8'h1b; // Escape ("esc" key)`
500			`12'h?29 : ascii <= 8'h20; // Space`
501			`12'h116 : ascii <= 8'h21; // !`
502			`12'h152 : ascii <= 8'h22; // "`
503			`12'h126 : ascii <= 8'h23; // #`
504			`12'h125 : ascii <= 8'h24; // $`
505			`12'h12e : ascii <= 8'h25; // %`
506			`12'h13d : ascii <= 8'h26; // &`
507			`12'h052 : ascii <= 8'h27; // '`
508			`12'h146 : ascii <= 8'h28; // (`
509			`12'h145 : ascii <= 8'h29; // )`
510			`12'h13e : ascii <= 8'h2a; // *`
511			`12'h155 : ascii <= 8'h2b; // +`
512			`12'h041 : ascii <= 8'h2c; // ,`
513			`12'h04e : ascii <= 8'h2d; // -`
514			`12'h049 : ascii <= 8'h2e; // .`
515			`12'h04a : ascii <= 8'h2f; // /`
516			`12'h045 : ascii <= 8'h30; // 0`
517			`12'h016 : ascii <= 8'h31; // 1`
518			`12'h01e : ascii <= 8'h32; // 2`
519			`12'h026 : ascii <= 8'h33; // 3`
520			`12'h025 : ascii <= 8'h34; // 4`
521			`12'h02e : ascii <= 8'h35; // 5`
522			`12'h036 : ascii <= 8'h36; // 6`
523			`12'h03d : ascii <= 8'h37; // 7`
524			`12'h03e : ascii <= 8'h38; // 8`
525			`12'h046 : ascii <= 8'h39; // 9`
526			`12'h14c : ascii <= 8'h3a; // :`
527			`12'h04c : ascii <= 8'h3b; // ;`
528			`12'h141 : ascii <= 8'h3c; // <`
529			`12'h055 : ascii <= 8'h3d; // =`
530			`12'h149 : ascii <= 8'h3e; // >`
531			`12'h14a : ascii <= 8'h3f; // ?`
532			`12'h11e : ascii <= 8'h40; // @`
533			`12'h11c : ascii <= 8'h41; // A`
534			`12'h132 : ascii <= 8'h42; // B`
535			`12'h121 : ascii <= 8'h43; // C`
536			`12'h123 : ascii <= 8'h44; // D`
537			`12'h124 : ascii <= 8'h45; // E`
538			`12'h12b : ascii <= 8'h46; // F`
539			`12'h134 : ascii <= 8'h47; // G`
540			`12'h133 : ascii <= 8'h48; // H`
541			`12'h143 : ascii <= 8'h49; // I`
542			`12'h13b : ascii <= 8'h4a; // J`
543			`12'h142 : ascii <= 8'h4b; // K`
544			`12'h14b : ascii <= 8'h4c; // L`
545			`12'h13a : ascii <= 8'h4d; // M`
546			`12'h131 : ascii <= 8'h4e; // N`
547			`12'h144 : ascii <= 8'h4f; // O`
548			`12'h14d : ascii <= 8'h50; // P`
549			`12'h115 : ascii <= 8'h51; // Q`
550			`12'h12d : ascii <= 8'h52; // R`
551			`12'h11b : ascii <= 8'h53; // S`
552			`12'h12c : ascii <= 8'h54; // T`
553			`12'h13c : ascii <= 8'h55; // U`
554			`12'h12a : ascii <= 8'h56; // V`
555			`12'h11d : ascii <= 8'h57; // W`
556			`12'h122 : ascii <= 8'h58; // X`
557			`12'h135 : ascii <= 8'h59; // Y`
558			`12'h11a : ascii <= 8'h5a; // Z`
559			`12'h054 : ascii <= 8'h5b; // [`
560			`12'h05d : ascii <= 8'h5c; // \`
561			`12'h05b : ascii <= 8'h5d; // ]`
562			`12'h136 : ascii <= 8'h5e; // ^`
563			`12'h14e : ascii <= 8'h5f; // _`
564			12'h00e : ascii <= 8'h60; // `
565			`12'h01c : ascii <= 8'h61; // a`
566			`12'h032 : ascii <= 8'h62; // b`
567			`12'h021 : ascii <= 8'h63; // c`
568			`12'h023 : ascii <= 8'h64; // d`
569			`12'h024 : ascii <= 8'h65; // e`
570			`12'h02b : ascii <= 8'h66; // f`
571			`12'h034 : ascii <= 8'h67; // g`
572			`12'h033 : ascii <= 8'h68; // h`
573			`12'h043 : ascii <= 8'h69; // i`
574			`12'h03b : ascii <= 8'h6a; // j`
575			`12'h042 : ascii <= 8'h6b; // k`
576			`12'h04b : ascii <= 8'h6c; // l`
577			`12'h03a : ascii <= 8'h6d; // m`
578			`12'h031 : ascii <= 8'h6e; // n`
579			`12'h044 : ascii <= 8'h6f; // o`
580			`12'h04d : ascii <= 8'h70; // p`
581			`12'h015 : ascii <= 8'h71; // q`
582			`12'h02d : ascii <= 8'h72; // r`
583			`12'h01b : ascii <= 8'h73; // s`
584			`12'h02c : ascii <= 8'h74; // t`
585			`12'h03c : ascii <= 8'h75; // u`
586			`12'h02a : ascii <= 8'h76; // v`
587			`12'h01d : ascii <= 8'h77; // w`
588			`12'h022 : ascii <= 8'h78; // x`
589			`12'h035 : ascii <= 8'h79; // y`
590			`12'h01a : ascii <= 8'h7a; // z`
591			`12'h154 : ascii <= 8'h7b; // {`
592			`12'h15d : ascii <= 8'h7c; // \|`
593			`12'h15b : ascii <= 8'h7d; // }`
594			`12'h10e : ascii <= 8'h7e; // ~`
595			`12'h?71 : ascii <= 8'h7f; // (Delete OR DEL on numeric keypad)`
596			`default : ascii <= 8'h2e; // '.' used for unlisted characters.`
597			`endcase`
598			`end`
599
600
601			`endmodule`
602
603			//`undefine TOTAL_BITS
604			//`undefine EXTEND_CODE
605			//`undefine RELEASE_CODE
606			//`undefine LEFT_SHIFT
607			//`undefine RIGHT_SHIFT
608