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[/] [z80control/] [trunk/] [DE1/] [rtl/] [VHDL/] [uart/] [clk_div.vhd] - Blame information for rev 12

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library IEEE;
use  IEEE.STD_LOGIC_1164.all;
use  IEEE.STD_LOGIC_ARITH.all;
use  IEEE.STD_LOGIC_UNSIGNED.all;
 
ENTITY clk_div IS
 
        PORT
        (
                clock_25Mhz                             : IN    STD_LOGIC;
                clock_1MHz                              : OUT   STD_LOGIC;
                clock_100KHz                    : OUT   STD_LOGIC;
                clock_10KHz                             : OUT   STD_LOGIC;
                clock_1KHz                              : OUT   STD_LOGIC;
                clock_100Hz                             : OUT   STD_LOGIC;
                clock_10Hz                              : OUT   STD_LOGIC;
                clock_1Hz                               : OUT   STD_LOGIC;
                clock_10sec                             : OUT   STD_LOGIC;
                clock_1min                              : OUT   STD_LOGIC;
                clock_1hr                               : OUT   STD_LOGIC);
 
END clk_div;
 
ARCHITECTURE a OF clk_div IS
 
        SIGNAL  count_1Mhz: STD_LOGIC_VECTOR(4 DOWNTO 0);
        SIGNAL  count_100Khz, count_10Khz, count_1Khz : STD_LOGIC_VECTOR(2 DOWNTO 0);
        SIGNAL  count_100hz, count_10hz, count_1hz : STD_LOGIC_VECTOR(2 DOWNTO 0);
        SIGNAL  count_10sec, count_1min, count_1hr : STD_LOGIC_VECTOR(2 DOWNTO 0);
 
        SIGNAL  clock_1Mhz_int, clock_100Khz_int, clock_10Khz_int, clock_1Khz_int: STD_LOGIC;
        SIGNAL  clock_100hz_int, clock_10Hz_int, clock_1Hz_int : STD_LOGIC;
        SIGNAL  clock_10sec_int, clock_1min_int, clock_1hr_int : STD_LOGIC;
 
BEGIN
        PROCESS
        BEGIN
-- Divide by 25
                WAIT UNTIL clock_25Mhz'EVENT and clock_25Mhz = '1';
                        IF count_1Mhz < 24 THEN
                                count_1Mhz <= count_1Mhz + 1;
                        ELSE
                                count_1Mhz <= "00000";
                        END IF;
                        IF count_1Mhz < 12 THEN
                                clock_1Mhz_int <= '0';
                        ELSE
                                clock_1Mhz_int <= '1';
                        END IF;
 
-- Ripple clocks are used in this code to save prescalar hardware
-- Sync all clock prescalar outputs back to master clock signal
                        clock_1Mhz <= clock_1Mhz_int;
                        clock_100Khz <= clock_100Khz_int;
                        clock_10Khz <= clock_10Khz_int;
                        clock_1Khz <= clock_1Khz_int;
                        clock_100hz <= clock_100hz_int;
                        clock_10hz <= clock_10hz_int;
                        clock_1hz <= clock_1hz_int;
                        clock_10sec <= clock_10sec_int;
                        clock_1min <= clock_1min_int;
                        clock_1hr <= clock_1hr_int;
        END PROCESS;
 
-- Divide by 10
        PROCESS
        BEGIN
                WAIT UNTIL clock_1Mhz_int'EVENT and clock_1Mhz_int = '1';
                        IF count_100Khz /= 4 THEN
                                count_100Khz <= count_100Khz + 1;
                        ELSE
                                count_100khz <= "000";
                                clock_100Khz_int <= NOT clock_100Khz_int;
                        END IF;
        END PROCESS;
 
-- Divide by 10
        PROCESS
        BEGIN
                WAIT UNTIL clock_100Khz_int'EVENT and clock_100Khz_int = '1';
                        IF count_10Khz /= 4 THEN
                                count_10Khz <= count_10Khz + 1;
                        ELSE
                                count_10khz <= "000";
                                clock_10Khz_int <= NOT clock_10Khz_int;
                        END IF;
        END PROCESS;
 
-- Divide by 10
        PROCESS
        BEGIN
                WAIT UNTIL clock_10Khz_int'EVENT and clock_10Khz_int = '1';
                        IF count_1Khz /= 4 THEN
                                count_1Khz <= count_1Khz + 1;
                        ELSE
                                count_1khz <= "000";
                                clock_1Khz_int <= NOT clock_1Khz_int;
                        END IF;
        END PROCESS;
 
-- Divide by 10
        PROCESS
        BEGIN
                WAIT UNTIL clock_1Khz_int'EVENT and clock_1Khz_int = '1';
                        IF count_100hz /= 4 THEN
                                count_100hz <= count_100hz + 1;
                        ELSE
                                count_100hz <= "000";
                                clock_100hz_int <= NOT clock_100hz_int;
                        END IF;
        END PROCESS;
 
-- Divide by 10
        PROCESS
        BEGIN
                WAIT UNTIL clock_100hz_int'EVENT and clock_100hz_int = '1';
                        IF count_10hz /= 4 THEN
                                count_10hz <= count_10hz + 1;
                        ELSE
                                count_10hz <= "000";
                                clock_10hz_int <= NOT clock_10hz_int;
                        END IF;
        END PROCESS;
 
-- Divide by 10
        PROCESS
        BEGIN
                WAIT UNTIL clock_10hz_int'EVENT and clock_10hz_int = '1';
                        IF count_1hz /= 4 THEN
                                count_1hz <= count_1hz + 1;
                        ELSE
                                count_1hz <= "000";
                                clock_1hz_int <= NOT clock_1hz_int;
                        END IF;
        END PROCESS;
 
-- Divide by 10
        PROCESS
        BEGIN
                WAIT UNTIL clock_1hz_int'EVENT and clock_1hz_int = '1';
                        IF count_10sec /= 4 THEN
                                count_10sec <= count_10sec + 1;
                        ELSE
                                count_10sec <= "000";
                                clock_10sec_int <= NOT clock_10sec_int;
                        END IF;
        END PROCESS;
 
-- Divide by 10
        PROCESS
        BEGIN
                WAIT UNTIL clock_10sec_int'EVENT and clock_10sec_int = '1';
                        IF count_1min /= 4 THEN
                                count_1min <= count_1min + 1;
                        ELSE
                                count_1min <= "000";
                                clock_1min_int <= NOT clock_1min_int;
                        END IF;
        END PROCESS;
 
-- Divide by 10
        PROCESS
        BEGIN
                WAIT UNTIL clock_1min_int'EVENT and clock_1min_int = '1';
                        IF count_1hr /= 4 THEN
                                count_1hr <= count_1hr + 1;
                        ELSE
                                count_1hr <= "000";
                                clock_1hr_int <= NOT clock_1hr_int;
                        END IF;
        END PROCESS;
 
END a;
 

Line No.	Rev	Author	Line
1	12	tylerapohl	`library IEEE;`
2			`use IEEE.STD_LOGIC_1164.all;`
3			`use IEEE.STD_LOGIC_ARITH.all;`
4			`use IEEE.STD_LOGIC_UNSIGNED.all;`
5
6			`ENTITY clk_div IS`
7
8			`PORT`
9			`(`
10			`clock_25Mhz : IN STD_LOGIC;`
11			`clock_1MHz : OUT STD_LOGIC;`
12			`clock_100KHz : OUT STD_LOGIC;`
13			`clock_10KHz : OUT STD_LOGIC;`
14			`clock_1KHz : OUT STD_LOGIC;`
15			`clock_100Hz : OUT STD_LOGIC;`
16			`clock_10Hz : OUT STD_LOGIC;`
17			`clock_1Hz : OUT STD_LOGIC;`
18			`clock_10sec : OUT STD_LOGIC;`
19			`clock_1min : OUT STD_LOGIC;`
20			`clock_1hr : OUT STD_LOGIC);`
21
22			`END clk_div;`
23
24			`ARCHITECTURE a OF clk_div IS`
25
26			`SIGNAL count_1Mhz: STD_LOGIC_VECTOR(4 DOWNTO 0);`
27			`SIGNAL count_100Khz, count_10Khz, count_1Khz : STD_LOGIC_VECTOR(2 DOWNTO 0);`
28			`SIGNAL count_100hz, count_10hz, count_1hz : STD_LOGIC_VECTOR(2 DOWNTO 0);`
29			`SIGNAL count_10sec, count_1min, count_1hr : STD_LOGIC_VECTOR(2 DOWNTO 0);`
30
31			`SIGNAL clock_1Mhz_int, clock_100Khz_int, clock_10Khz_int, clock_1Khz_int: STD_LOGIC;`
32			`SIGNAL clock_100hz_int, clock_10Hz_int, clock_1Hz_int : STD_LOGIC;`
33			`SIGNAL clock_10sec_int, clock_1min_int, clock_1hr_int : STD_LOGIC;`
34
35			`BEGIN`
36			`PROCESS`
37			`BEGIN`
38			`-- Divide by 25`
39			`WAIT UNTIL clock_25Mhz'EVENT and clock_25Mhz = '1';`
40			`IF count_1Mhz < 24 THEN`
41			`count_1Mhz <= count_1Mhz + 1;`
42			`ELSE`
43			`count_1Mhz <= "00000";`
44			`END IF;`
45			`IF count_1Mhz < 12 THEN`
46			`clock_1Mhz_int <= '0';`
47			`ELSE`
48			`clock_1Mhz_int <= '1';`
49			`END IF;`
50
51			`-- Ripple clocks are used in this code to save prescalar hardware`
52			`-- Sync all clock prescalar outputs back to master clock signal`
53			`clock_1Mhz <= clock_1Mhz_int;`
54			`clock_100Khz <= clock_100Khz_int;`
55			`clock_10Khz <= clock_10Khz_int;`
56			`clock_1Khz <= clock_1Khz_int;`
57			`clock_100hz <= clock_100hz_int;`
58			`clock_10hz <= clock_10hz_int;`
59			`clock_1hz <= clock_1hz_int;`
60			`clock_10sec <= clock_10sec_int;`
61			`clock_1min <= clock_1min_int;`
62			`clock_1hr <= clock_1hr_int;`
63			`END PROCESS;`
64
65			`-- Divide by 10`
66			`PROCESS`
67			`BEGIN`
68			`WAIT UNTIL clock_1Mhz_int'EVENT and clock_1Mhz_int = '1';`
69			`IF count_100Khz /= 4 THEN`
70			`count_100Khz <= count_100Khz + 1;`
71			`ELSE`
72			`count_100khz <= "000";`
73			`clock_100Khz_int <= NOT clock_100Khz_int;`
74			`END IF;`
75			`END PROCESS;`
76
77			`-- Divide by 10`
78			`PROCESS`
79			`BEGIN`
80			`WAIT UNTIL clock_100Khz_int'EVENT and clock_100Khz_int = '1';`
81			`IF count_10Khz /= 4 THEN`
82			`count_10Khz <= count_10Khz + 1;`
83			`ELSE`
84			`count_10khz <= "000";`
85			`clock_10Khz_int <= NOT clock_10Khz_int;`
86			`END IF;`
87			`END PROCESS;`
88
89			`-- Divide by 10`
90			`PROCESS`
91			`BEGIN`
92			`WAIT UNTIL clock_10Khz_int'EVENT and clock_10Khz_int = '1';`
93			`IF count_1Khz /= 4 THEN`
94			`count_1Khz <= count_1Khz + 1;`
95			`ELSE`
96			`count_1khz <= "000";`
97			`clock_1Khz_int <= NOT clock_1Khz_int;`
98			`END IF;`
99			`END PROCESS;`
100
101			`-- Divide by 10`
102			`PROCESS`
103			`BEGIN`
104			`WAIT UNTIL clock_1Khz_int'EVENT and clock_1Khz_int = '1';`
105			`IF count_100hz /= 4 THEN`
106			`count_100hz <= count_100hz + 1;`
107			`ELSE`
108			`count_100hz <= "000";`
109			`clock_100hz_int <= NOT clock_100hz_int;`
110			`END IF;`
111			`END PROCESS;`
112
113			`-- Divide by 10`
114			`PROCESS`
115			`BEGIN`
116			`WAIT UNTIL clock_100hz_int'EVENT and clock_100hz_int = '1';`
117			`IF count_10hz /= 4 THEN`
118			`count_10hz <= count_10hz + 1;`
119			`ELSE`
120			`count_10hz <= "000";`
121			`clock_10hz_int <= NOT clock_10hz_int;`
122			`END IF;`
123			`END PROCESS;`
124
125			`-- Divide by 10`
126			`PROCESS`
127			`BEGIN`
128			`WAIT UNTIL clock_10hz_int'EVENT and clock_10hz_int = '1';`
129			`IF count_1hz /= 4 THEN`
130			`count_1hz <= count_1hz + 1;`
131			`ELSE`
132			`count_1hz <= "000";`
133			`clock_1hz_int <= NOT clock_1hz_int;`
134			`END IF;`
135			`END PROCESS;`
136
137			`-- Divide by 10`
138			`PROCESS`
139			`BEGIN`
140			`WAIT UNTIL clock_1hz_int'EVENT and clock_1hz_int = '1';`
141			`IF count_10sec /= 4 THEN`
142			`count_10sec <= count_10sec + 1;`
143			`ELSE`
144			`count_10sec <= "000";`
145			`clock_10sec_int <= NOT clock_10sec_int;`
146			`END IF;`
147			`END PROCESS;`
148
149			`-- Divide by 10`
150			`PROCESS`
151			`BEGIN`
152			`WAIT UNTIL clock_10sec_int'EVENT and clock_10sec_int = '1';`
153			`IF count_1min /= 4 THEN`
154			`count_1min <= count_1min + 1;`
155			`ELSE`
156			`count_1min <= "000";`
157			`clock_1min_int <= NOT clock_1min_int;`
158			`END IF;`
159			`END PROCESS;`
160
161			`-- Divide by 10`
162			`PROCESS`
163			`BEGIN`
164			`WAIT UNTIL clock_1min_int'EVENT and clock_1min_int = '1';`
165			`IF count_1hr /= 4 THEN`
166			`count_1hr <= count_1hr + 1;`
167			`ELSE`
168			`count_1hr <= "000";`
169			`clock_1hr_int <= NOT clock_1hr_int;`
170			`END IF;`
171			`END PROCESS;`
172
173			`END a;`
174

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Subversion Repositories z80control

[/] [z80control/] [trunk/] [DE1/] [rtl/] [VHDL/] [uart/] [clk_div.vhd] - Blame information for rev 12