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tylerapohl |
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_arith.all;
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use IEEE.std_logic_unsigned.all;
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entity TOP_UART is
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port(
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-- Clocks
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CLOCK_27, -- 27 MHz
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CLOCK_50, -- 50 MHz
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EXT_CLOCK : in std_logic; -- External Clock
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-- Buttons and switches
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KEY : in std_logic_vector(3 downto 0); -- Push buttons
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SW : in std_logic_vector(9 downto 0); -- Switches
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-- LED displays
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HEX0, HEX1, HEX2, HEX3 -- 7-segment displays
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: out std_logic_vector(6 downto 0);
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LEDG : out std_logic_vector(7 downto 0); -- Green LEDs
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LEDR : out std_logic_vector(9 downto 0); -- Red LEDs
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-- RS-232 interface
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UART_TXD : out std_logic; -- UART transmitter
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UART_RXD : in std_logic; -- UART receiver
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-- IRDA interface
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-- IRDA_TXD : out std_logic; -- IRDA Transmitter
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IRDA_RXD : in std_logic; -- IRDA Receiver
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-- SDRAM
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DRAM_DQ : inout std_logic_vector(15 downto 0); -- Data Bus
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DRAM_ADDR : out std_logic_vector(11 downto 0); -- Address Bus
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DRAM_LDQM, -- Low-byte Data Mask
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DRAM_UDQM, -- High-byte Data Mask
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DRAM_WE_N, -- Write Enable
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DRAM_CAS_N, -- Column Address Strobe
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DRAM_RAS_N, -- Row Address Strobe
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DRAM_CS_N, -- Chip Select
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DRAM_BA_0, -- Bank Address 0
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DRAM_BA_1, -- Bank Address 0
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DRAM_CLK, -- Clock
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DRAM_CKE : out std_logic; -- Clock Enable
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-- FLASH
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FL_DQ : inout std_logic_vector(7 downto 0); -- Data bus
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FL_ADDR : out std_logic_vector(21 downto 0); -- Address bus
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FL_WE_N, -- Write Enable
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FL_RST_N, -- Reset
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FL_OE_N, -- Output Enable
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FL_CE_N : out std_logic; -- Chip Enable
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-- SRAM
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SRAM_DQ : inout std_logic_vector(15 downto 0); -- Data bus 16 Bits
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SRAM_ADDR : out std_logic_vector(17 downto 0); -- Address bus 18 Bits
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SRAM_UB_N, -- High-byte Data Mask
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SRAM_LB_N, -- Low-byte Data Mask
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SRAM_WE_N, -- Write Enable
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SRAM_CE_N, -- Chip Enable
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SRAM_OE_N : out std_logic; -- Output Enable
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-- SD card interface
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SD_DAT : in std_logic; -- SD Card Data SD pin 7 "DAT 0/DataOut"
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SD_DAT3 : out std_logic; -- SD Card Data 3 SD pin 1 "DAT 3/nCS"
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SD_CMD : out std_logic; -- SD Card Command SD pin 2 "CMD/DataIn"
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SD_CLK : out std_logic; -- SD Card Clock SD pin 5 "CLK"
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-- USB JTAG link
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TDI, -- CPLD -> FPGA (data in)
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TCK, -- CPLD -> FPGA (clk)
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TCS : in std_logic; -- CPLD -> FPGA (CS)
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TDO : out std_logic; -- FPGA -> CPLD (data out)
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-- I2C bus
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I2C_SDAT : inout std_logic; -- I2C Data
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I2C_SCLK : out std_logic; -- I2C Clock
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-- PS/2 port
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PS2_DAT, -- Data
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PS2_CLK : inout std_logic; -- Clock
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-- VGA output
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VGA_HS, -- H_SYNC
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VGA_VS : out std_logic; -- SYNC
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VGA_R, -- Red[3:0]
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VGA_G, -- Green[3:0]
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VGA_B : out std_logic_vector(3 downto 0); -- Blue[3:0]
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-- Audio CODEC
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AUD_ADCLRCK : inout std_logic; -- ADC LR Clock
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AUD_ADCDAT : in std_logic; -- ADC Data
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AUD_DACLRCK : inout std_logic; -- DAC LR Clock
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AUD_DACDAT : out std_logic; -- DAC Data
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AUD_BCLK : inout std_logic; -- Bit-Stream Clock
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AUD_XCK : out std_logic; -- Chip Clock
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-- General-purpose I/O
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GPIO_0, -- GPIO Connection 0
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GPIO_1 : inout std_logic_vector(35 downto 0) -- GPIO Connection 1
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);
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end TOP_UART;
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architecture rtl of TOP_UART is
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component miniUART
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port (
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SysClk : in Std_Logic; -- System Clock
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Reset : in Std_Logic; -- Reset input
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CS_N : in Std_Logic;
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RD_N : in Std_Logic;
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WR_N : in Std_Logic;
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RxD : in Std_Logic;
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TxD : out Std_Logic;
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IntRx_N : out Std_Logic; -- Receive interrupt
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IntTx_N : out Std_Logic; -- Transmit interrupt
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Addr : in Std_Logic_Vector(1 downto 0); --
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DataIn : in Std_Logic_Vector(7 downto 0); --
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DataOut : out Std_Logic_Vector(7 downto 0)); --
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end component;
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begin
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U1 : miniUART PORT MAP (
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SysClk => CLOCK_50, --: in Std_Logic; -- System Clock
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Reset => KEY(0), --: in Std_Logic; -- Reset input
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CS_N => SW(0), --: in Std_Logic;
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RD_N => SW(1), --: in Std_Logic;
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WR_N => SW(2), --: in Std_Logic;
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RxD => UART_RXD, --: in Std_Logic;
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TxD => UART_TXD, --: out Std_Logic;
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IntRx_N => LEDG(0), --: out Std_Logic; -- Receive interrupt
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IntTx_N => LEDG(1), --: out Std_Logic; -- Transmit interrupt
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Addr => SW(8 downto 7), --: in Std_Logic_Vector(1 downto 0); --
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DataIn => x"69", --: in Std_Logic_Vector(7 downto 0); --
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DataOut => LEDR(7 downto 0)--: out Std_Logic_Vector(7 downto 0)); --
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);
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--
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SRAM_DQ(15 downto 8) <= (others => 'Z');
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SRAM_ADDR(17 downto 16) <= "00";
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SRAM_UB_N <= '1';
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SRAM_LB_N <= '0';
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SRAM_CE_N <= '0';
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--
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UART_TXD <= 'Z';
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DRAM_ADDR <= (others => '0');
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DRAM_LDQM <= '0';
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DRAM_UDQM <= '0';
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DRAM_WE_N <= '1';
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DRAM_CAS_N <= '1';
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DRAM_RAS_N <= '1';
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DRAM_CS_N <= '1';
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DRAM_BA_0 <= '0';
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DRAM_BA_1 <= '0';
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DRAM_CLK <= '0';
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DRAM_CKE <= '0';
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FL_ADDR <= (others => '0');
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FL_WE_N <= '1';
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FL_RST_N <= '0';
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FL_OE_N <= '1';
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FL_CE_N <= '1';
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TDO <= '0';
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I2C_SCLK <= '0';
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AUD_DACDAT <= '0';
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AUD_XCK <= '0';
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-- Set all bidirectional ports to tri-state
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DRAM_DQ <= (others => 'Z');
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FL_DQ <= (others => 'Z');
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I2C_SDAT <= 'Z';
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AUD_ADCLRCK <= 'Z';
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AUD_DACLRCK <= 'Z';
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AUD_BCLK <= 'Z';
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GPIO_0 <= (others => 'Z');
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GPIO_1 <= (others => 'Z');
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end;
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