1 |
12 |
tylerapohl |
-------------------------------------------------------------------------------
|
2 |
|
|
-- Title : UART
|
3 |
|
|
-- Project : UART
|
4 |
|
|
-------------------------------------------------------------------------------
|
5 |
|
|
-- File : MiniUart.vhd
|
6 |
|
|
-- Author : Philippe CARTON
|
7 |
|
|
-- (philippe.carton2@libertysurf.fr)
|
8 |
|
|
-- Organization:
|
9 |
|
|
-- Created : 15/12/2001
|
10 |
|
|
-- Last update : 8/1/2003
|
11 |
|
|
-- Platform : Foundation 3.1i
|
12 |
|
|
-- Simulators : ModelSim 5.5b
|
13 |
|
|
-- Synthesizers: Xilinx Synthesis
|
14 |
|
|
-- Targets : Xilinx Spartan
|
15 |
|
|
-- Dependency : IEEE std_logic_1164, Rxunit.vhd, Txunit.vhd, utils.vhd
|
16 |
|
|
-------------------------------------------------------------------------------
|
17 |
|
|
-- Description: Uart (Universal Asynchronous Receiver Transmitter) for SoC.
|
18 |
|
|
-- Wishbone compatable.
|
19 |
|
|
-------------------------------------------------------------------------------
|
20 |
|
|
-- Copyright (c) notice
|
21 |
|
|
-- This core adheres to the GNU public license
|
22 |
|
|
--
|
23 |
|
|
-------------------------------------------------------------------------------
|
24 |
|
|
-- Revisions :
|
25 |
|
|
-- Revision Number :
|
26 |
|
|
-- Version :
|
27 |
|
|
-- Date :
|
28 |
|
|
-- Modifier : name <email>
|
29 |
|
|
-- Description :
|
30 |
|
|
--
|
31 |
|
|
------------------------------------------------------------------------------
|
32 |
|
|
|
33 |
|
|
library ieee;
|
34 |
|
|
use ieee.std_logic_1164.all;
|
35 |
|
|
|
36 |
|
|
entity UART is
|
37 |
|
|
generic(BRDIVISOR: INTEGER range 0 to 65535 := 1302); -- Baud rate divisor 130
|
38 |
|
|
port (
|
39 |
|
|
-- Wishbone signals
|
40 |
|
|
WB_CLK_I : in std_logic; -- clock
|
41 |
|
|
WB_RST_I : in std_logic; -- Reset input
|
42 |
|
|
WB_ADR_I : in std_logic_vector(1 downto 0); -- Adress bus
|
43 |
|
|
WB_DAT_I : in std_logic_vector(7 downto 0); -- DataIn Bus
|
44 |
|
|
WB_DAT_O : out std_logic_vector(7 downto 0); -- DataOut Bus
|
45 |
|
|
WB_WE_I : in std_logic; -- Write Enable
|
46 |
|
|
WB_STB_I : in std_logic; -- Strobe
|
47 |
|
|
WB_ACK_O : out std_logic; -- Acknowledge
|
48 |
|
|
-- process signals
|
49 |
|
|
IntTx_O : out std_logic; -- Transmit interrupt: indicate waiting for Byte
|
50 |
|
|
IntRx_O : out std_logic; -- Receive interrupt: indicate Byte received
|
51 |
|
|
BR_Clk_I : in std_logic; -- Clock used for Transmit/Receive
|
52 |
|
|
TxD_PAD_O: out std_logic; -- Tx RS232 Line
|
53 |
|
|
RxD_PAD_I: in std_logic); -- Rx RS232 Line
|
54 |
|
|
end UART;
|
55 |
|
|
|
56 |
|
|
-- Architecture for UART for synthesis
|
57 |
|
|
architecture Behaviour of UART is
|
58 |
|
|
|
59 |
|
|
component Counter
|
60 |
|
|
generic(COUNT: INTEGER range 0 to 65535); -- Count revolution
|
61 |
|
|
port (
|
62 |
|
|
Clk : in std_logic; -- Clock
|
63 |
|
|
Reset : in std_logic; -- Reset input
|
64 |
|
|
CE : in std_logic; -- Chip Enable
|
65 |
|
|
O : out std_logic); -- Output
|
66 |
|
|
end component;
|
67 |
|
|
|
68 |
|
|
component RxUnit
|
69 |
|
|
port (
|
70 |
|
|
Clk : in std_logic; -- system clock signal
|
71 |
|
|
Reset : in std_logic; -- Reset input
|
72 |
|
|
Enable : in std_logic; -- Enable input
|
73 |
|
|
ReadA : in Std_logic; -- Async Read Received Byte
|
74 |
|
|
RxD : in std_logic; -- RS-232 data input
|
75 |
|
|
RxAv : out std_logic; -- Byte available
|
76 |
|
|
DataO : out std_logic_vector(7 downto 0)); -- Byte received
|
77 |
|
|
end component;
|
78 |
|
|
|
79 |
|
|
component TxUnit
|
80 |
|
|
port (
|
81 |
|
|
Clk : in std_logic; -- Clock signal
|
82 |
|
|
Reset : in std_logic; -- Reset input
|
83 |
|
|
Enable : in std_logic; -- Enable input
|
84 |
|
|
LoadA : in std_logic; -- Asynchronous Load
|
85 |
|
|
TxD : out std_logic; -- RS-232 data output
|
86 |
|
|
Busy : out std_logic; -- Tx Busy
|
87 |
|
|
DataI : in std_logic_vector(7 downto 0)); -- Byte to transmit
|
88 |
|
|
end component;
|
89 |
|
|
|
90 |
|
|
signal RxData : std_logic_vector(7 downto 0); -- Last Byte received
|
91 |
|
|
signal TxData : std_logic_vector(7 downto 0); -- Last bytes transmitted
|
92 |
|
|
signal SReg : std_logic_vector(7 downto 0); -- Status register
|
93 |
|
|
signal EnabRx : std_logic; -- Enable RX unit
|
94 |
|
|
signal EnabTx : std_logic; -- Enable TX unit
|
95 |
|
|
signal RxAv : std_logic; -- Data Received
|
96 |
|
|
signal TxBusy : std_logic; -- Transmiter Busy
|
97 |
|
|
signal ReadA : std_logic; -- Async Read receive buffer
|
98 |
|
|
signal LoadA : std_logic; -- Async Load transmit buffer
|
99 |
|
|
signal Sig0 : std_logic; -- gnd signal
|
100 |
|
|
signal Sig1 : std_logic; -- vcc signal
|
101 |
|
|
--signal Counter : std_logic_vector(2 downto 0);
|
102 |
|
|
|
103 |
|
|
|
104 |
|
|
begin
|
105 |
|
|
sig0 <= '0';
|
106 |
|
|
sig1 <= '1';
|
107 |
|
|
Uart_Rxrate : Counter -- Baud Rate adjust
|
108 |
|
|
generic map (COUNT => BRDIVISOR)
|
109 |
|
|
port map (BR_CLK_I, sig0, sig1, EnabRx);
|
110 |
|
|
Uart_Txrate : Counter -- 4 Divider for Tx
|
111 |
|
|
generic map (COUNT => 4)
|
112 |
|
|
port map (BR_CLK_I, Sig0, EnabRx, EnabTx);
|
113 |
|
|
Uart_TxUnit : TxUnit port map (BR_CLK_I, WB_RST_I, EnabTX, LoadA, TxD_PAD_O, TxBusy, TxData);
|
114 |
|
|
Uart_RxUnit : RxUnit port map (BR_CLK_I, WB_RST_I, EnabRX, ReadA, RxD_PAD_I, RxAv, RxData);
|
115 |
|
|
IntTx_O <= not TxBusy;
|
116 |
|
|
IntRx_O <= RxAv;
|
117 |
|
|
SReg(0) <= not TxBusy;
|
118 |
|
|
SReg(1) <= RxAv;
|
119 |
|
|
SReg(7 downto 2) <= "000000";
|
120 |
|
|
|
121 |
|
|
-- Implements WishBone data exchange.
|
122 |
|
|
-- Clocked on rising edge. Synchronous Reset RST_I
|
123 |
|
|
WBctrl : process(WB_CLK_I, WB_RST_I, WB_STB_I, WB_WE_I, WB_ADR_I)
|
124 |
|
|
variable StatM : std_logic_vector(4 downto 0);
|
125 |
|
|
begin
|
126 |
|
|
if Rising_Edge(WB_CLK_I) then
|
127 |
|
|
if (WB_RST_I = '1') then
|
128 |
|
|
ReadA <= '0';
|
129 |
|
|
LoadA <= '0';
|
130 |
|
|
else
|
131 |
|
|
if (WB_STB_I = '1' and WB_WE_I = '1' and WB_ADR_I = "00") then -- Write Byte to Tx
|
132 |
|
|
TxData <= WB_DAT_I;
|
133 |
|
|
LoadA <= '1'; -- Load signal
|
134 |
|
|
else LoadA <= '0';
|
135 |
|
|
end if;
|
136 |
|
|
if (WB_STB_I = '1' and WB_WE_I = '0' and WB_ADR_I = "00") then -- Read Byte from Rx
|
137 |
|
|
ReadA <= '1'; -- Read signal
|
138 |
|
|
else ReadA <= '0';
|
139 |
|
|
end if;
|
140 |
|
|
end if;
|
141 |
|
|
end if;
|
142 |
|
|
end process;
|
143 |
|
|
WB_ACK_O <= WB_STB_I;
|
144 |
|
|
WB_DAT_O <=
|
145 |
|
|
RxData when WB_ADR_I = "00" else -- Read Byte from Rx
|
146 |
|
|
SReg when WB_ADR_I = "01" else -- Read Status Reg
|
147 |
|
|
"00000000";
|
148 |
|
|
end Behaviour;
|