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[/] [z80soc/] [branches/] [RonivonCosta/] [DE1/] [rtl/] [VHDL/] [VIDEO_80X40.vhd] - Blame information for rev 41

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Line No. Rev Author Line
1 11 rrred
library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_unsigned.all;
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-- use IEEE.std_logic_arith.all;
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use IEEE.numeric_std.all;
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--use IEEE.std_logic_signed.all;
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--use IEEE.math_real.all;
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--use IEEE.math_complex.all;
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ENTITY video_80x40 is
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        PORT(   CLOCK_50                : IN STD_LOGIC;
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                        VRAM_DATA               : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
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                        VRAM_ADDR               : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
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                        VRAM_CLOCK              : OUT STD_LOGIC;
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                        VRAM_WREN               : OUT STD_LOGIC;
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                        VGA_R,
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                        VGA_G,
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                        VGA_B                   : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
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                        VGA_HS,
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                        VGA_VS                  : OUT STD_LOGIC);
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END video_80x40;
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ARCHITECTURE A OF video_80x40 IS
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        -- Added for VDU support
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        signal Clock_video              : std_logic;
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        signal VGA_R_sig                : std_logic_vector(3 downto 0);
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        signal VGA_G_sig                : std_logic_vector(3 downto 0);
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        signal VGA_B_sig                : std_logic_vector(3 downto 0);
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        signal pixel_row_sig    : std_logic_vector(9 downto 0);
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        signal pixel_column_sig : std_logic_vector(9 downto 0);
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        signal pixel_clock_sig  : std_logic;
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        signal char_addr_sig    : std_logic_vector(7 downto 0);
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        signal font_row_sig             : std_logic_vector(2 downto 0);
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        signal font_col_sig             : std_logic_vector(2 downto 0);
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        signal pixel_sig                : std_logic;
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        signal video_on_sig             : std_logic;
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BEGIN
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        VGA_R_sig <= "0000";
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        VGA_G_sig <= "0000";
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        VGA_B_sig <= pixel_sig & pixel_sig & pixel_sig & pixel_sig;
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        VRAM_WREN <= video_on_sig;
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        VRAM_CLOCK <= pixel_clock_sig;
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        VRAM_ADDR <= (pixel_row_sig(9 downto 4) * "0101000" + pixel_column_sig(9 downto 4));
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        -- Fonts ROM read
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        char_addr_sig <= VRAM_DATA;
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        font_row_sig(2 downto 0) <= pixel_row_sig(3 downto 1);
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        font_col_sig(2 downto 0) <= pixel_column_sig(3 downto 1);
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        vga_sync_inst : work.vga_sync
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                port map (
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                        clock_50Mhz                     => CLOCK_50,
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                        red                                     => VGA_R_sig,
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                        green                           => VGA_G_sig,
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                        blue                            => VGA_B_sig,
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                        red_out                         => VGA_R,
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                        green_out                       => VGA_G,
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                        blue_out                        => VGA_B,
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                        horiz_sync_out          => VGA_HS,
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                        vert_sync_out           => VGA_VS,
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                        video_on                        => video_on_sig,
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                        pixel_clock                     => pixel_clock_sig,
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                        pixel_row                       => pixel_row_sig,
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                        pixel_column            => pixel_column_sig
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        );
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        char_rom_inst : work.char_rom
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                port map (
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                        clock                           => pixel_clock_sig,
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                        character_address       => char_addr_sig,
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                        font_row                        => font_row_sig,
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                        font_col                        => font_col_sig,
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                        rom_mux_output          => pixel_sig
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        );
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END A;

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