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[/] [z80soc/] [branches/] [RonivonCosta/] [DE1/] [rtl/] [VHDL/] [t80/] [DebugSystemXR.vhd] - Blame information for rev 41

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-- Z80, Monitor ROM, external SRAM interface and two 16450 UARTs
-- that can be synthesized and used with
-- the NoICE debugger that can be found at
-- http://www.noicedebugger.com/
 
library IEEE;
use IEEE.std_logic_1164.all;
 
entity DebugSystemXR is
        port(
                Reset_n         : in std_logic;
                Clk                     : in std_logic;
                NMI_n           : in std_logic;
                OE_n            : out std_logic;
                WE_n            : out std_logic;
                RAMCS_n         : out std_logic;
                ROMCS_n         : out std_logic;
                PGM_n           : out std_logic;
                A                       : out std_logic_vector(16 downto 0);
                D                       : inout std_logic_vector(7 downto 0);
                RXD0            : in std_logic;
                CTS0            : in std_logic;
                DSR0            : in std_logic;
                RI0                     : in std_logic;
                DCD0            : in std_logic;
                RXD1            : in std_logic;
                CTS1            : in std_logic;
                DSR1            : in std_logic;
                RI1                     : in std_logic;
                DCD1            : in std_logic;
                TXD0            : out std_logic;
                RTS0            : out std_logic;
                DTR0            : out std_logic;
                TXD1            : out std_logic;
                RTS1            : out std_logic;
                DTR1            : out std_logic
        );
end entity DebugSystemXR;
 
architecture struct of DebugSystemXR is
 
        signal M1_n                     : std_logic;
        signal MREQ_n           : std_logic;
        signal IORQ_n           : std_logic;
        signal RD_n                     : std_logic;
        signal WR_n                     : std_logic;
        signal RFSH_n           : std_logic;
        signal HALT_n           : std_logic;
        signal WAIT_n           : std_logic;
        signal INT_n            : std_logic;
        signal RESET_s          : std_logic;
        signal BUSRQ_n          : std_logic;
        signal BUSAK_n          : std_logic;
        signal A_i                      : std_logic_vector(15 downto 0);
        signal D_i                      : std_logic_vector(7 downto 0);
        signal ROM_D            : std_logic_vector(7 downto 0);
        signal UART0_D          : std_logic_vector(7 downto 0);
        signal UART1_D          : std_logic_vector(7 downto 0);
        signal CPU_D            : std_logic_vector(7 downto 0);
 
        signal Mirror           : std_logic;
 
        signal IOWR_n           : std_logic;
        signal RAMCS_n_i        : std_logic;
        signal UART0CS_n        : std_logic;
        signal UART1CS_n        : std_logic;
 
        signal BaudOut0         : std_logic;
        signal BaudOut1         : std_logic;
 
begin
 
        Wait_n <= '1';
        BusRq_n <= '1';
        INT_n <= '1';
 
        OE_n <= RD_n;
        WE_n <= WR_n;
        RAMCS_n <= RAMCS_n_i;
        ROMCS_n <= '1';
        PGM_n <= '1';
        A(14 downto 0) <= A_i(14 downto 0);
        A(16 downto 15) <= "00";
        D <= D_i when WR_n = '0' else "ZZZZZZZZ";
 
        process (Reset_n, Clk)
        begin
                if Reset_n = '0' then
                        Reset_s <= '0';
                        Mirror <= '0';
                elsif Clk'event and Clk = '1' then
                        Reset_s <= '1';
                        if IORQ_n = '0' and A_i(7 downto 4) = "1111" then
                                Mirror <= D_i(0);
                        end if;
                end if;
        end process;
 
        IOWR_n <= WR_n or IORQ_n;
        RAMCS_n_i <= (not Mirror and not A_i(15)) or MREQ_n;
        UART0CS_n <= '0' when IORQ_n = '0' and A_i(7 downto 3) = "00000" else '1';
        UART1CS_n <= '0' when IORQ_n = '0' and A_i(7 downto 3) = "10000" else '1';
 
        CPU_D <=
                D when RAMCS_n_i = '0' else
                UART0_D when UART0CS_n = '0' else
                UART1_D when UART1CS_n = '0' else
                ROM_D;
 
        u0 : entity work.T80s
                        generic map(Mode => 1, T2Write => 1, IOWait => 0)
                        port map(
                                RESET_n => RESET_s,
                                CLK_n => Clk,
                                WAIT_n => WAIT_n,
                                INT_n => INT_n,
                                NMI_n => NMI_n,
                                BUSRQ_n => BUSRQ_n,
                                M1_n => M1_n,
                                MREQ_n => MREQ_n,
                                IORQ_n => IORQ_n,
                                RD_n => RD_n,
                                WR_n => WR_n,
                                RFSH_n => RFSH_n,
                                HALT_n => HALT_n,
                                BUSAK_n => BUSAK_n,
                                A => A_i,
                                DI => CPU_D,
                                DO => D_i);
 
        u1 : entity work.MonZ80
                        port map(
                                Clk => Clk,
                                A => A_i(10 downto 0),
                                D => ROM_D);
 
        u3 : entity work.T16450
                        port map(
                                MR_n => Reset_s,
                                XIn => Clk,
                                RClk => BaudOut0,
                                CS_n => UART0CS_n,
                                Rd_n => RD_n,
                                Wr_n => IOWR_n,
                                A => A_i(2 downto 0),
                                D_In => D_i,
                                D_Out => UART0_D,
                                SIn => RXD0,
                                CTS_n => CTS0,
                                DSR_n => DSR0,
                                RI_n => RI0,
                                DCD_n => DCD0,
                                SOut => TXD0,
                                RTS_n => RTS0,
                                DTR_n => DTR0,
                                OUT1_n => open,
                                OUT2_n => open,
                                BaudOut => BaudOut0,
                                Intr => open);
 
        u4 : entity work.T16450
                        port map(
                                MR_n => Reset_s,
                                XIn => Clk,
                                RClk => BaudOut1,
                                CS_n => UART1CS_n,
                                Rd_n => RD_n,
                                Wr_n => IOWR_n,
                                A => A_i(2 downto 0),
                                D_In => D_i,
                                D_Out => UART1_D,
                                SIn => RXD1,
                                CTS_n => CTS1,
                                DSR_n => DSR1,
                                RI_n => RI1,
                                DCD_n => DCD1,
                                SOut => TXD1,
                                RTS_n => RTS1,
                                DTR_n => DTR1,
                                OUT1_n => open,
                                OUT2_n => open,
                                BaudOut => BaudOut1,
                                Intr => open);
 
end;

Line No.	Rev	Author	Line
1	11	rrred	`-- Z80, Monitor ROM, external SRAM interface and two 16450 UARTs`
2			`-- that can be synthesized and used with`
3			`-- the NoICE debugger that can be found at`
4			`-- http://www.noicedebugger.com/`
5
6			`library IEEE;`
7			`use IEEE.std_logic_1164.all;`
8
9			`entity DebugSystemXR is`
10			`port(`
11			`Reset_n : in std_logic;`
12			`Clk : in std_logic;`
13			`NMI_n : in std_logic;`
14			`OE_n : out std_logic;`
15			`WE_n : out std_logic;`
16			`RAMCS_n : out std_logic;`
17			`ROMCS_n : out std_logic;`
18			`PGM_n : out std_logic;`
19			`A : out std_logic_vector(16 downto 0);`
20			`D : inout std_logic_vector(7 downto 0);`
21			`RXD0 : in std_logic;`
22			`CTS0 : in std_logic;`
23			`DSR0 : in std_logic;`
24			`RI0 : in std_logic;`
25			`DCD0 : in std_logic;`
26			`RXD1 : in std_logic;`
27			`CTS1 : in std_logic;`
28			`DSR1 : in std_logic;`
29			`RI1 : in std_logic;`
30			`DCD1 : in std_logic;`
31			`TXD0 : out std_logic;`
32			`RTS0 : out std_logic;`
33			`DTR0 : out std_logic;`
34			`TXD1 : out std_logic;`
35			`RTS1 : out std_logic;`
36			`DTR1 : out std_logic`
37			`);`
38			`end entity DebugSystemXR;`
39
40			`architecture struct of DebugSystemXR is`
41
42			`signal M1_n : std_logic;`
43			`signal MREQ_n : std_logic;`
44			`signal IORQ_n : std_logic;`
45			`signal RD_n : std_logic;`
46			`signal WR_n : std_logic;`
47			`signal RFSH_n : std_logic;`
48			`signal HALT_n : std_logic;`
49			`signal WAIT_n : std_logic;`
50			`signal INT_n : std_logic;`
51			`signal RESET_s : std_logic;`
52			`signal BUSRQ_n : std_logic;`
53			`signal BUSAK_n : std_logic;`
54			`signal A_i : std_logic_vector(15 downto 0);`
55			`signal D_i : std_logic_vector(7 downto 0);`
56			`signal ROM_D : std_logic_vector(7 downto 0);`
57			`signal UART0_D : std_logic_vector(7 downto 0);`
58			`signal UART1_D : std_logic_vector(7 downto 0);`
59			`signal CPU_D : std_logic_vector(7 downto 0);`
60
61			`signal Mirror : std_logic;`
62
63			`signal IOWR_n : std_logic;`
64			`signal RAMCS_n_i : std_logic;`
65			`signal UART0CS_n : std_logic;`
66			`signal UART1CS_n : std_logic;`
67
68			`signal BaudOut0 : std_logic;`
69			`signal BaudOut1 : std_logic;`
70
71			`begin`
72
73			`Wait_n <= '1';`
74			`BusRq_n <= '1';`
75			`INT_n <= '1';`
76
77			`OE_n <= RD_n;`
78			`WE_n <= WR_n;`
79			`RAMCS_n <= RAMCS_n_i;`
80			`ROMCS_n <= '1';`
81			`PGM_n <= '1';`
82			`A(14 downto 0) <= A_i(14 downto 0);`
83			`A(16 downto 15) <= "00";`
84			`D <= D_i when WR_n = '0' else "ZZZZZZZZ";`
85
86			`process (Reset_n, Clk)`
87			`begin`
88			`if Reset_n = '0' then`
89			`Reset_s <= '0';`
90			`Mirror <= '0';`
91			`elsif Clk'event and Clk = '1' then`
92			`Reset_s <= '1';`
93			`if IORQ_n = '0' and A_i(7 downto 4) = "1111" then`
94			`Mirror <= D_i(0);`
95			`end if;`
96			`end if;`
97			`end process;`
98
99			`IOWR_n <= WR_n or IORQ_n;`
100			`RAMCS_n_i <= (not Mirror and not A_i(15)) or MREQ_n;`
101			`UART0CS_n <= '0' when IORQ_n = '0' and A_i(7 downto 3) = "00000" else '1';`
102			`UART1CS_n <= '0' when IORQ_n = '0' and A_i(7 downto 3) = "10000" else '1';`
103
104			`CPU_D <=`
105			`D when RAMCS_n_i = '0' else`
106			`UART0_D when UART0CS_n = '0' else`
107			`UART1_D when UART1CS_n = '0' else`
108			`ROM_D;`
109
110			`u0 : entity work.T80s`
111			`generic map(Mode => 1, T2Write => 1, IOWait => 0)`
112			`port map(`
113			`RESET_n => RESET_s,`
114			`CLK_n => Clk,`
115			`WAIT_n => WAIT_n,`
116			`INT_n => INT_n,`
117			`NMI_n => NMI_n,`
118			`BUSRQ_n => BUSRQ_n,`
119			`M1_n => M1_n,`
120			`MREQ_n => MREQ_n,`
121			`IORQ_n => IORQ_n,`
122			`RD_n => RD_n,`
123			`WR_n => WR_n,`
124			`RFSH_n => RFSH_n,`
125			`HALT_n => HALT_n,`
126			`BUSAK_n => BUSAK_n,`
127			`A => A_i,`
128			`DI => CPU_D,`
129			`DO => D_i);`
130
131			`u1 : entity work.MonZ80`
132			`port map(`
133			`Clk => Clk,`
134			`A => A_i(10 downto 0),`
135			`D => ROM_D);`
136
137			`u3 : entity work.T16450`
138			`port map(`
139			`MR_n => Reset_s,`
140			`XIn => Clk,`
141			`RClk => BaudOut0,`
142			`CS_n => UART0CS_n,`
143			`Rd_n => RD_n,`
144			`Wr_n => IOWR_n,`
145			`A => A_i(2 downto 0),`
146			`D_In => D_i,`
147			`D_Out => UART0_D,`
148			`SIn => RXD0,`
149			`CTS_n => CTS0,`
150			`DSR_n => DSR0,`
151			`RI_n => RI0,`
152			`DCD_n => DCD0,`
153			`SOut => TXD0,`
154			`RTS_n => RTS0,`
155			`DTR_n => DTR0,`
156			`OUT1_n => open,`
157			`OUT2_n => open,`
158			`BaudOut => BaudOut0,`
159			`Intr => open);`
160
161			`u4 : entity work.T16450`
162			`port map(`
163			`MR_n => Reset_s,`
164			`XIn => Clk,`
165			`RClk => BaudOut1,`
166			`CS_n => UART1CS_n,`
167			`Rd_n => RD_n,`
168			`Wr_n => IOWR_n,`
169			`A => A_i(2 downto 0),`
170			`D_In => D_i,`
171			`D_Out => UART1_D,`
172			`SIn => RXD1,`
173			`CTS_n => CTS1,`
174			`DSR_n => DSR1,`
175			`RI_n => RI1,`
176			`DCD_n => DCD1,`
177			`SOut => TXD1,`
178			`RTS_n => RTS1,`
179			`DTR_n => DTR1,`
180			`OUT1_n => open,`
181			`OUT2_n => open,`
182			`BaudOut => BaudOut1,`
183			`Intr => open);`
184
185			`end;`

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[/] [z80soc/] [branches/] [RonivonCosta/] [DE1/] [rtl/] [VHDL/] [t80/] [DebugSystemXR.vhd] - Blame information for rev 41