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--
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-- Z80 compatible microprocessor core
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--
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-- Version : 0247
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--
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-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
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--
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-- All rights reserved
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--
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-- Redistribution and use in source and synthezised forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--
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-- Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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--
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-- Redistributions in synthesized form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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--
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-- Neither the name of the author nor the names of other contributors may
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-- be used to endorse or promote products derived from this software without
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-- specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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-- Please report bugs to the author, but before you do so, please
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-- make sure that this is not a derivative work and that
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-- you have the latest version of this file.
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--
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-- The latest version of this file can be found at:
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-- http://www.opencores.org/cvsweb.shtml/t80/
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--
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-- Limitations :
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--
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-- File history :
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--
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-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
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--
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-- 0238 : Fixed zero flag for 16 bit SBC and ADC
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--
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-- 0240 : Added GB operations
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--
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-- 0242 : Cleanup
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--
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-- 0247 : Cleanup
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--
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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entity T80_ALU is
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generic(
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Mode : integer := 0;
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Flag_C : integer := 0;
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Flag_N : integer := 1;
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Flag_P : integer := 2;
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Flag_X : integer := 3;
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Flag_H : integer := 4;
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Flag_Y : integer := 5;
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Flag_Z : integer := 6;
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Flag_S : integer := 7
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);
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port(
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Arith16 : in std_logic;
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Z16 : in std_logic;
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ALU_Op : in std_logic_vector(3 downto 0);
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IR : in std_logic_vector(5 downto 0);
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ISet : in std_logic_vector(1 downto 0);
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BusA : in std_logic_vector(7 downto 0);
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BusB : in std_logic_vector(7 downto 0);
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F_In : in std_logic_vector(7 downto 0);
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Q : out std_logic_vector(7 downto 0);
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F_Out : out std_logic_vector(7 downto 0)
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);
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end T80_ALU;
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architecture rtl of T80_ALU is
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procedure AddSub(A : std_logic_vector;
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B : std_logic_vector;
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Sub : std_logic;
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Carry_In : std_logic;
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signal Res : out std_logic_vector;
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signal Carry : out std_logic) is
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variable B_i : unsigned(A'length - 1 downto 0);
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variable Res_i : unsigned(A'length + 1 downto 0);
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begin
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if Sub = '1' then
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B_i := not unsigned(B);
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else
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B_i := unsigned(B);
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end if;
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Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
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Carry <= Res_i(A'length + 1);
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Res <= std_logic_vector(Res_i(A'length downto 1));
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end;
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-- AddSub variables (temporary signals)
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signal UseCarry : std_logic;
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signal Carry7_v : std_logic;
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signal Overflow_v : std_logic;
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signal HalfCarry_v : std_logic;
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signal Carry_v : std_logic;
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signal Q_v : std_logic_vector(7 downto 0);
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signal BitMask : std_logic_vector(7 downto 0);
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begin
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with IR(5 downto 3) select BitMask <= "00000001" when "000",
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"00000010" when "001",
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"00000100" when "010",
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"00001000" when "011",
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"00010000" when "100",
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"00100000" when "101",
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"01000000" when "110",
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"10000000" when others;
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UseCarry <= not ALU_Op(2) and ALU_Op(0);
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AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
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AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
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AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
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OverFlow_v <= Carry_v xor Carry7_v;
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process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
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variable Q_t : std_logic_vector(7 downto 0);
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variable DAA_Q : unsigned(8 downto 0);
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begin
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Q_t := "--------";
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F_Out <= F_In;
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DAA_Q := "---------";
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case ALU_Op is
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when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
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F_Out(Flag_N) <= '0';
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F_Out(Flag_C) <= '0';
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case ALU_OP(2 downto 0) is
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when "000" | "001" => -- ADD, ADC
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Q_t := Q_v;
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F_Out(Flag_C) <= Carry_v;
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F_Out(Flag_H) <= HalfCarry_v;
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F_Out(Flag_P) <= OverFlow_v;
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when "010" | "011" | "111" => -- SUB, SBC, CP
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Q_t := Q_v;
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F_Out(Flag_N) <= '1';
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F_Out(Flag_C) <= not Carry_v;
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F_Out(Flag_H) <= not HalfCarry_v;
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F_Out(Flag_P) <= OverFlow_v;
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when "100" => -- AND
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Q_t(7 downto 0) := BusA and BusB;
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F_Out(Flag_H) <= '1';
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when "101" => -- XOR
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Q_t(7 downto 0) := BusA xor BusB;
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F_Out(Flag_H) <= '0';
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when others => -- OR "110"
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Q_t(7 downto 0) := BusA or BusB;
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F_Out(Flag_H) <= '0';
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end case;
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if ALU_Op(2 downto 0) = "111" then -- CP
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F_Out(Flag_X) <= BusB(3);
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F_Out(Flag_Y) <= BusB(5);
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else
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F_Out(Flag_X) <= Q_t(3);
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F_Out(Flag_Y) <= Q_t(5);
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end if;
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if Q_t(7 downto 0) = "00000000" then
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F_Out(Flag_Z) <= '1';
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if Z16 = '1' then
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F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC
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end if;
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else
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F_Out(Flag_Z) <= '0';
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end if;
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F_Out(Flag_S) <= Q_t(7);
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case ALU_Op(2 downto 0) is
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when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
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when others =>
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F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
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Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
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end case;
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if Arith16 = '1' then
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F_Out(Flag_S) <= F_In(Flag_S);
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F_Out(Flag_Z) <= F_In(Flag_Z);
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F_Out(Flag_P) <= F_In(Flag_P);
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end if;
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when "1100" =>
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-- DAA
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F_Out(Flag_H) <= F_In(Flag_H);
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F_Out(Flag_C) <= F_In(Flag_C);
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DAA_Q(7 downto 0) := unsigned(BusA);
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DAA_Q(8) := '0';
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if F_In(Flag_N) = '0' then
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-- After addition
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-- Alow > 9 or H = 1
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if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
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if (DAA_Q(3 downto 0) > 9) then
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F_Out(Flag_H) <= '1';
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else
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F_Out(Flag_H) <= '0';
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end if;
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DAA_Q := DAA_Q + 6;
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end if;
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-- new Ahigh > 9 or C = 1
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if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
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DAA_Q := DAA_Q + 96; -- 0x60
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end if;
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else
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-- After subtraction
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if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
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if DAA_Q(3 downto 0) > 5 then
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F_Out(Flag_H) <= '0';
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end if;
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DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
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end if;
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if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
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DAA_Q := DAA_Q - 352; -- 0x160
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end if;
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end if;
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F_Out(Flag_X) <= DAA_Q(3);
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F_Out(Flag_Y) <= DAA_Q(5);
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F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
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Q_t := std_logic_vector(DAA_Q(7 downto 0));
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if DAA_Q(7 downto 0) = "00000000" then
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F_Out(Flag_Z) <= '1';
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else
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F_Out(Flag_Z) <= '0';
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end if;
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F_Out(Flag_S) <= DAA_Q(7);
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F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
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DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
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when "1101" | "1110" =>
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-- RLD, RRD
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Q_t(7 downto 4) := BusA(7 downto 4);
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if ALU_Op(0) = '1' then
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Q_t(3 downto 0) := BusB(7 downto 4);
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else
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Q_t(3 downto 0) := BusB(3 downto 0);
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end if;
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F_Out(Flag_H) <= '0';
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F_Out(Flag_N) <= '0';
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F_Out(Flag_X) <= Q_t(3);
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F_Out(Flag_Y) <= Q_t(5);
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if Q_t(7 downto 0) = "00000000" then
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F_Out(Flag_Z) <= '1';
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else
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F_Out(Flag_Z) <= '0';
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end if;
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F_Out(Flag_S) <= Q_t(7);
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F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
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Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
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when "1001" =>
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-- BIT
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Q_t(7 downto 0) := BusB and BitMask;
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F_Out(Flag_S) <= Q_t(7);
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if Q_t(7 downto 0) = "00000000" then
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F_Out(Flag_Z) <= '1';
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| 267 |
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F_Out(Flag_P) <= '1';
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else
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F_Out(Flag_Z) <= '0';
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F_Out(Flag_P) <= '0';
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end if;
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F_Out(Flag_H) <= '1';
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| 273 |
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F_Out(Flag_N) <= '0';
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| 274 |
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F_Out(Flag_X) <= '0';
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| 275 |
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F_Out(Flag_Y) <= '0';
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| 276 |
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if IR(2 downto 0) /= "110" then
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| 277 |
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F_Out(Flag_X) <= BusB(3);
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| 278 |
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F_Out(Flag_Y) <= BusB(5);
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| 279 |
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end if;
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when "1010" =>
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-- SET
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Q_t(7 downto 0) := BusB or BitMask;
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| 283 |
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when "1011" =>
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-- RES
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| 285 |
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Q_t(7 downto 0) := BusB and not BitMask;
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| 286 |
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when "1000" =>
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| 287 |
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-- ROT
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| 288 |
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case IR(5 downto 3) is
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| 289 |
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when "000" => -- RLC
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| 290 |
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Q_t(7 downto 1) := BusA(6 downto 0);
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| 291 |
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Q_t(0) := BusA(7);
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| 292 |
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F_Out(Flag_C) <= BusA(7);
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| 293 |
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when "010" => -- RL
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| 294 |
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Q_t(7 downto 1) := BusA(6 downto 0);
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| 295 |
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Q_t(0) := F_In(Flag_C);
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| 296 |
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F_Out(Flag_C) <= BusA(7);
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| 297 |
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when "001" => -- RRC
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| 298 |
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Q_t(6 downto 0) := BusA(7 downto 1);
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| 299 |
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Q_t(7) := BusA(0);
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| 300 |
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F_Out(Flag_C) <= BusA(0);
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| 301 |
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when "011" => -- RR
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| 302 |
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Q_t(6 downto 0) := BusA(7 downto 1);
|
| 303 |
|
|
Q_t(7) := F_In(Flag_C);
|
| 304 |
|
|
F_Out(Flag_C) <= BusA(0);
|
| 305 |
|
|
when "100" => -- SLA
|
| 306 |
|
|
Q_t(7 downto 1) := BusA(6 downto 0);
|
| 307 |
|
|
Q_t(0) := '0';
|
| 308 |
|
|
F_Out(Flag_C) <= BusA(7);
|
| 309 |
|
|
when "110" => -- SLL (Undocumented) / SWAP
|
| 310 |
|
|
if Mode = 3 then
|
| 311 |
|
|
Q_t(7 downto 4) := BusA(3 downto 0);
|
| 312 |
|
|
Q_t(3 downto 0) := BusA(7 downto 4);
|
| 313 |
|
|
F_Out(Flag_C) <= '0';
|
| 314 |
|
|
else
|
| 315 |
|
|
Q_t(7 downto 1) := BusA(6 downto 0);
|
| 316 |
|
|
Q_t(0) := '1';
|
| 317 |
|
|
F_Out(Flag_C) <= BusA(7);
|
| 318 |
|
|
end if;
|
| 319 |
|
|
when "101" => -- SRA
|
| 320 |
|
|
Q_t(6 downto 0) := BusA(7 downto 1);
|
| 321 |
|
|
Q_t(7) := BusA(7);
|
| 322 |
|
|
F_Out(Flag_C) <= BusA(0);
|
| 323 |
|
|
when others => -- SRL
|
| 324 |
|
|
Q_t(6 downto 0) := BusA(7 downto 1);
|
| 325 |
|
|
Q_t(7) := '0';
|
| 326 |
|
|
F_Out(Flag_C) <= BusA(0);
|
| 327 |
|
|
end case;
|
| 328 |
|
|
F_Out(Flag_H) <= '0';
|
| 329 |
|
|
F_Out(Flag_N) <= '0';
|
| 330 |
|
|
F_Out(Flag_X) <= Q_t(3);
|
| 331 |
|
|
F_Out(Flag_Y) <= Q_t(5);
|
| 332 |
|
|
F_Out(Flag_S) <= Q_t(7);
|
| 333 |
|
|
if Q_t(7 downto 0) = "00000000" then
|
| 334 |
|
|
F_Out(Flag_Z) <= '1';
|
| 335 |
|
|
else
|
| 336 |
|
|
F_Out(Flag_Z) <= '0';
|
| 337 |
|
|
end if;
|
| 338 |
|
|
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
|
| 339 |
|
|
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
|
| 340 |
|
|
if ISet = "00" then
|
| 341 |
|
|
F_Out(Flag_P) <= F_In(Flag_P);
|
| 342 |
|
|
F_Out(Flag_S) <= F_In(Flag_S);
|
| 343 |
|
|
F_Out(Flag_Z) <= F_In(Flag_Z);
|
| 344 |
|
|
end if;
|
| 345 |
|
|
when others =>
|
| 346 |
|
|
null;
|
| 347 |
|
|
end case;
|
| 348 |
|
|
Q <= Q_t;
|
| 349 |
|
|
end process;
|
| 350 |
|
|
|
| 351 |
|
|
end;
|
